Independently programmable memory segments within a PMOS...

Details Independently programmable memory segments within a PMOS... Independently programmable memory segments within a PMOS...

2001-10-08

2003-01-07

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S339000, C257S341000

Reexamination Certificate

active

06504191

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of semiconductor devices. Specifically this invention identifies an enhancement of P-channel Electrically Erasable Programmable Read Only Memory (EEPROM) (hereinafter memory) devices as disclosed by the prior art wherein the device is segmented into independently programmable memory sub-arrays. Thus, the present invention is an improvement on the semiconductor memory devices disclosed by the prior art.
2. Description of the Related Art
The relevant prior art is identified as U.S. patent application Ser. No. 08/890,415 filed Jul. 9, 1997, entitled “Low Voltage Single Supply CMOS Electrically Erasable Read-Only Memory” which is a continuation-in-part of U.S. patent application Ser. No. 08/778,315, filed Jan. 2, 1997 and issued as U.S. Pat. No. 5,790,455. U.S. patent application Ser. No. 08/890,415 (Caywood 2), filed Jul. 9, 1997 and U.S. Pat. No. 5,790,455 (Caywood 1) are incorporated by reference.
Before Caywood, a common practice was to produce N-channel cells over a P-well substrate because of a simpler manufacturing process and lower programming voltages. The Caywood approach produces precisely the opposite configuration, i.e. P-channel devices over an N-well, which itself resides in a P-type substrate. The novelty of the Caywood approach is the reduction in magnitude of the applied voltage required for erasing and writing to the device while maintaining a similar writing speed as found in the art prior to Caywood as well as the elimination of certain components functionally necessary in the prior art.
Referring to
FIG. 1
, the N-channel memory device art prior to Caywood is illustrated. Each memory transistor (MEM) required a row select transistor (SEL), which controlled the data received from the bit lines (BL). Also, if byte addressing was desired, then the device included a byte select transistor (BYTE) for every eight memory transistors. The problem solved by Caywood with the advent of P-channel/N-well device was the elimination of the row select transistors. Even after Caywood, byte selection still required the presence of the byte select transistors. The elimination of the byte select transistors resulted in the undesirable effect that the entire row must be reprogrammed following an erase operation.
Referring to
FIG. 2
, the Caywood approach is illustrated in general terms for a single memory transistor
1
. The N-well
3
is created within a P-type substrate
2
. The P-channel for the drain
4
and source
5
is created within the N-well
3
. Poly
1
or the floating gate
6
of the memory transistor
1
is created after the active region for the drain
4
and source
5
. Poly2 or the control electrode
7
of the memory transistor is fabricated over the floating gate. Various non-conductive layers
8
insulate the P-channel
4
and
5
, the floating gate
6
and the control electrode
7
from each other.
FIG. 3
illustrates a plurality of cell rows
100
, typically connected to gate electrodes of memory transistors and a plurality of columns
200
typically connected to source and drain electrodes of memory transistors in the array, with both cell rows and cell columns existing on a single N-well
300
substrate. The limitation to the Caywood P-channel memory arrays, as shown in
FIG. 3
, is that all memory cells in any particular row must selected, thus written or erased, during a particular operation.
Alternatively stated, in the prior art as disclosed by Caywood, the cell rows are not segmented such that some memory cells in the cell row may be selected for writing while other memory cells in the row are not. Thus, in order to program the contents of a single memory cell, the entire cell row must then be programmed in order to change the data in one memory cell.
In many applications it is desired to change the data in the memory array, one byte at a time. In the N-channel device prior art, this feature was accomplished by the inclusion of a byte select transistor (BYTE) for each eight memory transistors as shown in FIG.
1
. The disadvantage of this approach is the increased demand for silicon area to accommodate the overhead of the byte select transistor (BYTE). For example, from solely a transistor perspective, a byte select transistor (BYTE) for every eight memory transistors requires an 11% overhead (i.e. 1/9).
Moreover, the capability of changing one byte at a time would give an endurance advantage over row select memory arrays because only one byte of cells would need to undergo the electrical stress of the programming cycle as opposed to the entire row. It is well known to those skilled in the art of semiconductor memory fabrication that one cause of EEPROM failure is attributable to excessive erase/write operations.
Therefore a need exists to provide a technique whereby the advantages of P-channel/N-well EEPROM technology are maximized by providing independently programmable memory segments within the EEPROM array other than with byte select transistors.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a P-channel/N-well electrically erasable programmable read only memory array that is divided into independently programmable memory segments.
It is another object of the present invention to provide a plurality of independently programmable memory segments within a memory array by fabricating a plurality of N-wells within the substrate of the array or by segmenting the N-well of the array into sub-wells.
It is another object of the present invention to provide a P-channel/N-well electrically erasable programmable read only memory device with independently programmable memory segments without the necessity for byte select transistors.
It is another object of the present invention to provide one or more methods for creating a plurality of N-wells or segmenting the N-well of the array. One method of creating a plurality of N-wells within a substrate is referred to as p-n junction isolation. A method for segmenting the N-well of the memory array is referred to as dielectric isolation.
In accordance with one embodiment of the present invention, a memory array comprises a plurality of N-wells within a P-type substrate and a plurality of independently programmable memory segments. Each independently programmable memory segment is comprised of M memory cell columns and N memory cell rows. Each independently programmable memory segment resides within a unique and separate N-well. Thus, each N-well contains an independently programmable memory segment.
The method of creating the plurality of N-wells within the P-type substrate comprises the steps of growing a buffer oxide on a P-type substrate, applying photoresist to the buffer oxide, etching the photoresist to form a plurality of N-well channels and implanting N-wells via the N-well channels.
In accordance with another embodiment of the present invention, a memory array comprises an N-well within a P-type substrate wherein the N-well is segmented in to a plurality of electrically isolated sub N-wells, M memory transistor columns within each of the plurality of electrically isolated sub N-wells and N memory transistor rows within each of the plurality of electrically isolated sub N-wells.
The method of fabricating the sub-wells from a single N-well comprises the steps of implanting a P-type substrate to form a single N-well, applying photoresist over the single N-well, etching the photoresist to form a plurality of apertures, etching a plurality of trenches via the plurality of apertures with a trench depth which exceeds that of the N-well and which penetrates the P-type substrate to form a plurality of electrically isolated sub N-wells, and filling the plurality of trenches with an insulating material wherein the insulating material prevents electrical conduction as between each of the plurality of electrically isolated sub N-wells.


REFERENCES:
patent: 4318751 (1982-03-01), Horng
patent: 4933295 (1990-06-01), Feist
patent: 5170374 (1992-12-01), Shimohigashi et al.
patent:

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