Independently non-homogeneously dynamically reconfigurable two d

Details Independently non-homogeneously dynamically reconfigurable two d Independently non-homogeneously dynamically reconfigurable two d

1994-09-20

2000-11-07

Maung, Zarni

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

712 11, 712 10, 710 2, G06F 1300

Patent

active

061450723

ABSTRACT:
In a SIMD architecture having a two dimensional array of processing elements, where a controller broadcasts instructions to all processing elements in the array, a dynamically reconfigurable switching means useful to connect four of the processing elements in the array into a group in accordance with either the broadcast instruction of the controller or a special communication instruction held in one processing element of the group, the switch includes at least one dataline connected to each processing element in the group. A multiplexer is connected to each data line and to the controller and to a configuration register. It is adapted to load the special communication instruction from the one processing element in the group into a configuration register and to operate in accord with either the broadcast instruction from the controller or the contents of the configuration register to select one of the four data lines as a source of data and applying the data therefrom to a source output port. A demultiplexer is connected to each data line and to the controller and to said configuration register, and to the source output port of the multiplexer means, and adapted to operate in accord with either the broadcast instruction from the controller or the contents of the configuration register to select one of the four data lines as a source of data and applying the data therefrom to a selected data line. The switch also acts to connect processing elements that cross chip partitions forming the processor array. Up to four such switches can be used to connect a group of four processing elements.

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