Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-09-12
2004-12-14
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230010, C365S230030, C365S230080
Reexamination Certificate
active
06831873
ABSTRACT:
BACKGROUND OF THE INVENTION
Virtually every modem computing device incorporates at least one, and typically several memory devices for storing instructions and data. The computing device may be a personal computer (PC), a dedicated-use device such as a telecommunications switch, or a mobile device such as a web-enabled wireless personal digital assistant (PDA). These are only examples, of course, many other computing devices are available. Each will usually include a read only memory (ROM) for storing instructions needed for starting up the device when power is first supplied. As its name implies, a ROM is typically not written to—although programmable variations of the basic ROM are available. ROM memory is non-volatile, meaning that the information stored on it is not lost when the power is turned off. It is precisely this non-volatile quality, of course, that permits the ROM to reliably store the device's start-up instructions.
Because the ROM cannot ordinarily be written to, or at least easily reprogrammed, it is of little use for storage of information that frequently changes. (There is also typically a limit to the number of times that a programmable ROM can be reliably re-programmed.) Frequently changing information includes, for example, data and program instructions associated with word processing documents, spreadsheets, routing tables, retrieved web pages. For long-term storage of such items, a hard drive, floppy disc, tape, or even a compact disc may be used. Such devices provide satisfactory means for long-term (and non-volatile) storage, but require relatively significant time for read and write operations, and are therefore less than satisfactory for currently-running applications, especially those that require numerous memory-access operations such as games.
One of the factors that makes disc or tape-drive memories relatively slow, of course, is the need to move physical media during the read and write processes. Much faster therefore are solid state memory devices. The previously-discussed ROM is one example of such devices. For rapid access to stored data, another solid-state memory device called random access memory (RAM) is often used. These devices use an organized plurality of transistors, and sometimes capacitors in order to store individual bits of data. A supply of electricity is necessary in order for this storage to be maintained, and therefore such devices are said to be volatile in nature. That is, when electrical power is lost, the stored information is lost as well. While this can certainly be a disadvantage under some circumstances, the speed of access associated with RAM devices and their relatively inexpensive cost of construction make them ideal for storing data related to running applications. The basic operation of these RAM devices will now be covered as part of the background of the invention.
As mentioned above, the RAM device is made up of a large number of individual electrical components. The components used may vary to some extent, but in general there are two basic types of RAM. The first uses an array of independently accessible transistors, and the electrical state of each individual set of transistors making up a memory location determines its contents. This type of RAM is called “static RAM” (SRAM) because the contents of each memory location remains unchanged as long as power is applied, or until it is rewritten. The second type of RAM uses a series of transistors, each having an associated capacitor. Each such individual pair of components forms a separate memory location, and has an associated address assigned as being in a particular row and column of an array. The state of the capacitor as containing a charge (or not) indicates the state (one or zero) of the particular memory location. The transistors are used to control application of electrical current to the capacitor. Capacitors are subject to lose their charge over time, however, and so any capacitor whose assigned state requires that it store an electrical charge must be periodically “refreshed” so that it does not revert to its uncharged state. Because the capacitors in this type of RAM must be periodically refreshed, it is referred to as a dynamic RAM (DRAM). (As will be seen below, the present invention is of particular advantage when used with a DRAM.) Both types of RAM devices perform essentially the same function in slightly different ways. Capacitors being smaller and less expensive to manufacture than transistors, however, DRAM devices are often more desirable despite the need for a refresh cycle.
There are several types of DRAM devices. In general, the different types represent attempts to make the memory device faster in operation through some design enhancement. One such type is the synchronous DRAM (SDRAM), which synchronizes its read and write operations according to the cycles of the system clock, allowing much quicker operation. SDRAMs are becoming increasingly popular for this reason and are used in a great many devices. Despite the increase in operating speed, however, the SDRAMs still require a periodic refresh cycle in order to maintain the integrity of the stored data.
FIG. 1A
shows a simplified SDRAM memory module. The memory module
100
, a term used herein for convenience, will generally be said to include at least a memory controller
105
connected to an actual SDRAM by a data bus
110
for transporting data back and forth, address bus
110
for specifying the address to read or write the data from and control bus
120
for the transmission of control signals. The memory controller
105
is usually connected directly to the computing devices central processor (not shown). In an alternate embodiment, the memory controller
105
may actually be manufactured as part of the central processing unit (CPU) itself.
FIG. 1B
is a simplified block diagram illustrating a basic memory module according to an alternate design, one that uses multiple memory banks. According to this configuration, memory module
150
includes memory controller
155
, which controls SDRAM memory banks
180
and
185
through control bus
170
. Control bus
170
, as well as data bus
160
and address bus
165
are of course coupled with the memory controller
155
itself and with both SDRAM memory banks. Note that although two memory banks are shown, there could be many.
Generally speaking, memory controllers such as memory controller
105
in FIG.
1
A and memory controller
155
in
FIG. 1B
are microchips designed and sold specifically for this purpose. They often have other functions as well, but their function with regard to data and instruction storage is to receive instructions from the computing device's central processing unit and to direct which information is to be stored in, or retrieved from memory. Likewise, SDRAM devices are often designed as individual memory chips or portions of a chip set. The use of multiple banks of SDRAM, such as is illustrated in
FIG. 1B
, allows a designer/manufacturer to increase memory size simply by adding another stock SDRAM device, rather than having to design and build one that is uniquely suitable for the application at hand. The number of SDRAM memory banks that can be employed is often limited by the ability of the memory controller to separately address each available memory location.
Unfortunately, where the memory controller does perform other functions, its operation may be interrupted by the need for a reset related to one of those other functions. Even where no other function is being utilized, any reset or interruption in the refresh control signals generated by the memory controller will result in a loss of the data and instructions stored in the SDRAM, whether or not the system power has actually failed or not. Of great advantage in such instances would be a device or method of preserving the information stored on the SDRAM or multiple SDRAM banks even in the event that the main memory controller is unable to send appropriate control signals to direct the SDRAM memory to continue its refresh cycle. The prese
Alcatel
Elms Richard
Hoersten Craig A.
Luu Pho M.
Sewell V. Lawrence
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