Incrementing subtractive circuits

Details Incrementing subtractive circuits Incrementing subtractive circuits

1990-04-05

1992-04-14

Malzahn, David H.

Boots, shoes, and leggings

364770, G06F 750

Patent

active

051053799

ABSTRACT:
An incrementing subtractive circuit for use in digital signal processing is constituted by a full adder having data inputs of which at least one is inverted, a sum output, and a carry output which is coupled by way of a half adder circuit to a one bit upshifter at the carry input of the full adder. The one bit upshifter is controlled by a least significant bit control signal. The half adder includes a carry recirculation loop adapted to add a logical unity in response to the least significant bit control signal. The arrangement has the effect of adding integer two to the carry value of the full adder and achieves the additional incrementing necessary for the performance of incrementing subtraction or negating addition.

REFERENCES:
patent: 3816734 (1974-06-01), Brendzel
patent: 3941990 (1976-03-01), Rabasse
patent: 4218751 (1980-08-01), McManigal
Smith & Denyer, Serial Data Computation, Kluwer Academic Press, 1988, pp. 59-65.
Halijak, "Binary Subtraction by Double Complemented Addition", Comput. & Elect. Engng., vol. 4, Pergamon Press, 1977, Printed in Great Britain, pp. 251-254.
"A Bit-Level Pipelined Implementation of a C-CMOS Multiplier-Accumulator Using a New Pipelined Full-Adder Cell Design", Mar., 1989.

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