Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-09-20
2004-01-13
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06678711
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally concerns a circuit for incrementing or decrementing a first input quantity by a second input quantity, depending upon the value of an increment/decrement input signal.
2. Description of the Related Art
An incrementer/decrementer circuit conventionally is used to increment or decrement a first input quantity by a second input quantity, with an increment/decrement signal determining whether the second input quantity is added to or subtracted from the first input quantity. Conventionally, an incrementer/decrementer circuit is implemented using an adder and a combination of gates. For example, a common conventional incrementer/decrementer circuit is illustrated in FIG.
1
.
As shown in
FIG. 1
, incrementer/decrementer circuit
20
includes an adder
22
. Adder
22
has the following inputs: a n-bit first input
24
, a n-bit second input
26
, and a 1-bit carry-in input
28
. Adder
22
also includes n-bit summation output
30
and a 1-bit carry-out output
32
. Not shown in
FIG. 1
is a clock signal input which signals when the addition is to take place. Upon input of the appropriate clock signal, adder
22
adds the n-bit signal at input
24
to the n-bit signal at input
26
and the 1-bit carry-in signal at input
28
, with the 1-bit carry-in signal corresponding to the least significant bit of the addition. The results of this addition are output as n-bit output signal
30
and a 1-bit carry-out signal
32
. Typically, n will be 4, 8,16 or 32, but can be any whole number.
To convert adder
22
into an incrementer/decrementer circuit, it is common to combine the increment/decrement quantity
36
with an increment/decrement signal using a number of gates prior to inputting that signal into input
26
. Thus, as shown in
FIG. 1
, each bit of the n-bit increment/decrement quantity
36
is combined with a 1-bit increment/decrement signal
38
in plural exclusive-or gates
40
. Although only a single exclusive-or gate
40
is shown in
FIG. 1
, it should be understood that this is done for simplicity of illustration only and that the notation in
FIG. 1
should be understood to indicate that a separate exclusive-or gate is used for each bit of the n-bit quantity
36
. That is, each bit of quantity
36
is combined with the one-bit increment/decrement signal
38
is a separate exclusive-or gate
40
. The resulting bits
37
are then supplied to input
26
of adder
22
. Thus, n separate exclusive-or gates must be provided and the increment/decrement signal
38
must be capable of driving all n of such exclusive-or gates. As shown in
FIG. 1
, increment/decrement signal
38
also is supplied to carry-in input
28
. Finally, increment/decrement signal
38
also is combined with carry-out signal
32
in exclusive-or gate
42
to produce the true carry-out signal
44
.
It is initially noted that in the configuration shown in
FIG. 1
, when the increment/decrement signal
38
is set to zero, the quantity
36
is added to quantity
46
and when increment/decrement signal
38
is set to one, quantity
36
is subtracted from quantity
46
. Thus, combining an input bit with the increment/decrement signal
38
in an exclusive-or gate
40
results in the input bit passing through unchanged in the event that increment has been selected and results in an inversion of the input bit when decrement has been selected. Therefore, the quantity
37
which is provided to input
26
is identical to quantity
36
when “increment” has been selected and is the inversion of quantity
36
when “decrement” has been selected. When “increment” has been selected, quantity
36
is therefore added directly to quantity
46
, the carry-in bit provided to input
28
is zero, and the carry-out bit signal
44
is identical to the carry-out signal
32
. Thus, in this situation increment/decrement circuit
20
functions exactly as adder
22
with no carry-in signal.
On the other hand, when the increment/decrement signal
38
is set to one, quantity
37
, which is then the inversion of quantity
36
, is added to a carry-in bit of one and to quantity
46
. It can be shown that the result of this addition is the same as subtracting quantity
36
from quantity
46
, except that the carry-out bit will be inverted. Therefore, in this case the increment/decrement signal
38
inverts the carry-out bit at output
32
to provide the correct carry-out bit at output
44
.
While the increment/decrement circuit shown in
FIG. 1
works for its intended purpose, the present inventor has discovered a more efficient way to implement an increment/decrement circuit.
SUMMARY OF THE INVENTION
In one aspect, the present invention is directed to an incrementing/decrementing apparatus that includes an adder having a first input and a second input, each of the first input and the second input comprising multiple bits. A first multi-bit signal is connected to the first input, and a second multi-bit signal is connected to the second input, the second multi-bit signal including multiple bits. The adder increments the first multi-bit signal by a quantity when an increment/decrement signal has a first value and decrements the first multi-bit signal by the quantity when the increment/decrement signal has a second value. The multiple bits of the second multi-bit signal include at least one bit based solely on a corresponding bit in the quantity and at least one bit based solely on a value of the increment/decrement signal.
As described in more detail below, by basing at least one bit of such multi-bit signal solely on a corresponding bit in the quantity and at least one bit solely on the increment/decrement signal, the present invention often can significantly reduce the number of gates required to implement the incrementer/decrementer circuit.
In a further aspect, the invention is directed to an incrementing/decrementing apparatus that includes an adder having a first input and a second input, each of the first input and the second input including multiple bits. A first multi-bit signal is connected to the first input, and a second multi-bit signal connected to the second input, the second multi-bit signal including multiple bits. The adder increments the first multi-bit signal by a quantity when an increment/decrement signal has a first value and decrements the first multi-bit signal by the quantity when the increment/decrement signal has a second value. The multiple bits of the second multi-bit signal have been specified by comparing bits of the quantity to corresponding bits of a two's complement of the quantity.
As described in more detail below, by specifying the bits of the second multi-bit signal in the foregoing manner, the present invention often can significantly reduce the number of gates required to implement the incrementer/decrementer circuit.
In a still further aspect, the invention is directed to determining bits for a multi-bit signal by obtaining a quantity that includes multiple bits and calculating a two's complement of the quantity. Then, each bit position of a multi-bit signal is assigned a value based on a comparison of a corresponding bit position in the quantity to the corresponding bit position in the two's complement of the quantity.
REFERENCES:
patent: 4280190 (1981-07-01), Smith
patent: 4486851 (1984-12-01), Christopher et al.
patent: 5027310 (1991-06-01), Dalrymple
patent: 5835394 (1998-11-01), Wong
patent: 5889693 (1999-03-01), Joshi et al.
patent: 6516335 (2003-02-01), Martin et al.
Reza Hashemina, Highly Parallel Increment/Decrement using CMOS technology, 1991, IEEE, pp. 866-869.*
Reza Hashemina, A New Parallel Technigue for Design of Decrement/Decrement and Two's Complement Circuits, 1992, IEEE, pp. 887-890.
Do Chat C.
LSI Logic Corporation
Mitchell Silberberg & Knupp LLP
Ngo Chuong Dinh
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