Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2011-04-26
2011-04-26
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Reexamination Certificate
active
07934180
ABSTRACT:
An incremental speculative merge structure which enables the elimination of invalid merge candidates without requiring the discarding of the speculative merge structure and all verification results obtained upon that structure. Targets are provided for validating the equivalence of gates g1iand g2i, and the fanout references of g1iand g2iare provided to a controllable multiplexer set to output g1i. Upon determining nonequivalence of g2i, of failing to proved equivalence, the multiplexer is switched to output the g1ifanout reference, thus undoing the incremental speculative merge.
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Baumgartner Jason
Kanzelman Robert
Mony Hari
Paruthi Viresh
Brevetto Law Group
Chiang Jack
International Business Machines - Corporation
Parihar Suchin
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