Reexamination Certificate
1998-05-26
2001-06-19
Teska, Kevin J. (Department: 2768)
Reexamination Certificate
active
06247853
ABSTRACT:
DESCRIPTION
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to yield estimation techniques for large complex circuit designs and, more particularly, to an incremental method for critical area computation of via blocks in very large scale integrated (VLSI) circuits.
2. Background Description
Very large scale integrated (VLSI) circuit yield prediction is based on the concept of critical area which reflects the sensitivity of the chip to defects occurring during the manufacturing process. A via block is a missing material defect that overlaps with a via and thus destroys its connectivity. Via blocks occur frequently during fabrication and thus computing the critical area fast is an important problem in yield prediction.
PROBLEM SOLVED BY THIS INVENTION
Yield prediction is of growing importance in modern VLSI design due to the need for reducing the cost of manufacturing. Yield estimation techniques for large complex designs are based on the concept of critical area which provides an analytical formulation for yield loss caused by defects occurring during fabrication.
For examples of state of the art yield prediction techniques, see, W. Maly and J. Deszczka, “Yield Estimation Model for VLSI Artwork Evaluation”,
Electron Lett.,
vol 19, no.6, pp. 226-22, March 1983, C. H. Stapper, “Modeling of Defects in Integrated Circuits Photolithographic Patterns”,
IBM J. Research and Development,
vol.28, no.4, pp. 461-475, 1984, W. Maly, “Modeling of lithography related yield losses for CAD of VLSI circuits”,
IEEE Transactions on Computer-Aided Design,
vol. CAD-4, no 3, pp. 166-177, July 1985, A. V. Ferris-Prabhu, “Modeling the Critical Area in Yield Forecast”,
IEEE Journal of Solid State Circuits,
vol. SC-20, No. 4, August 1985, pp. 874-878, J. Pineda de Gyvez, C. Di,
IEEE Transactions on Computer-Aided Design,
vol.11, no 5, pp. 638-658, May 1992, I. A. Wagner and I. Koren, “An Interactive VLSI CAD Tool for Yield Estimation”,
IEEE Transactions on Semiconductor Manufacturing,
Vol.8, No.2, 1995, pp. 130-138, and C. H. Stapper and R. S. Rosner, “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation”,
IEEE Transactions on Semiconductor Manufacturing,
Vol.8, No.2, 1995, pp. 95-101. Fabrication defects are caused by contaminants in materials and equipment. I. Bubel, W. Maly, T. Wass, P. Nag, H. Hartman, D. Schmitt-Landsiedel, S. Griep, “AFFCA: A Tool for Critical Area Analysis with Circular Defects and Lithography Deformed Layout”,
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems,
November 1995, pp. 10-18, A. R. Datal, P. D. Franzon, M. J. Lorenzetti, “A layout-driven yield predictor and fault generator for VLSII”,
IEEE Transactions on Semiconductor Manufacturing,
Vol.6, No.1, 1993, S. Gandemer, B. C. Tremintin, and J. J. Chariot, “Critical Area and critical levels calculation in IC yield modeling”,
IEEE Transactions on Electronic Devices,
vol.35, no. 2, pp. 158-166, February 1988, W. Maly, “Computer Aided Design for VLSI Circuit Manufacturability”,
Proc. IEEE,
Vol 78, No.2, February 1990, pp. 356-390, and H. Walker an S. W. Director, “VLASIC: A yield simulator for integrated circuits”,
IEEE Transactions on Computer Aided Design,
vol. CAD-S, no. 4, pp. 541-556, October 1986.
From Wagner and Koren, supra, the formula used to compute critical area is the following:
A
c
=
∫
0
∞
Area
(
CR
(
r
)
)
D
(
r
)
ⅆ
r
(
1
)
where A
c
denotes the critical area, CR(r) denotes the critical region, i.e., the region in which the center of a defect of size r must fall in order to cause circuit failure, and D(r) is the density function of the defect size. Area(CR(r)) denotes the area of the critical region. Based on experimental data, D(r) is given by the following formula:
D
(
r
)
=
{
cr
q
r
0
q
+
1
,
0
≤
r
≤
r
0
,
cr
0
p
-
1
r
p
,
r
0
≤
r
≤
∞
}
where p, q are real numbers (typically p=3, q=1)
c
=
(
q
+
1
)
(
p
-
1
)
(
q
+
p
)
and r
0
is some minimum optically resolvable size. See Stapper, supra, and A. V. Ferris-Prabhu, “Defect size variations and their effect on the critical area of VLSI devices”,
IEEE Journal of Solid State Circuits,
vol. SC-20, No. 4, August 1985, pp. 878-880, and I. Koren, “The effect of scaling on the yield of VLSI circuits”,
Yield Modeling and Defect Tolerance in VLSI Circuits,
W. R. Moore, W. Maly, and A. Strojwas Eds., Bristol UK: Adam-Hilger Ltd., 1988, pp. 91-99.
Essentially, there are two types of contamination causing manufacturing defects: extra material causing shorts between different conducting regions and missing material causing open circuits. Via blocks are missing material defects that overlap with vias and thus destroy the connection between elements of the same net in different layers. Among the missing material defects via blocks occur very frequently and thus computing their critical area is important for yield prediction.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a new efficient method to compute critical area and critical regions for via blocks.
The method according to the invention is incremental and takes advantage of the hierarchy in the design. In order to increase the efficiency further, the L
∞
or the L
1
metric is used instead of the Euclidean geometry. The present invention includes three major steps:
1. Model defects as “circles” in other than Euclidean geometries; e.g., the L
∞
geometry. For example, the “unit circle” in the L
∞
geometry is a square of side two. Modeling defects as squares instead of circles can make the computation easier and more efficient.
2. Characterize the critical region of a via shape for several geometries as a function of the defect size. In certain geometries (including the Euclidean), the critical region of one via shape grows uniformly as the defect radius increases.
3. Based on these characterizations, provide an incremental algorithm to compute critical area for via blocks which is valid for several geometries. The incremental computation is efficient because it takes advantage of the hierarchical structure typical of VLSI designs, in which repeated geometric patterns are represented by cells consisting of shapes and transforms on usages of those cells.
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Wagner and Koren “An Interactive VLSI CAD Tool for Yield Estimation,” IEEE Transactions on Semiconductor Manufacturing, vol. 8, No. 2, May 1995, p. 130-138.*
Dalal et al. “A Layout-Driven Yield Predictor and Fault Generator for VLSI,” IEEE Transactions on Semiconductor Manufacturing,vol. 6, No. 1, Feb. 1993, p. 77-82.*
Stapper and Rosner “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation,” IEEE Transactions on Semiconductor Manufacturing, vol. 8, No. 2 May 1995, p. 95-102.*
Hess and Troele “Modeling of Real Defect Outlines and Parameter Extraction Using a Checkerboard Test Structure to Localize Defects,” IEEE Transactions on Semiconductor Manufacturing, vol. 7, No. 3, Aug. 1994, p. 284-292.
Allen Archibald John
Lavin Mark Alan
Papadopoulou Evanthia
Tellez Gustavo Enrique
Garbowski Leigh Marie
International Business Machines - Corporation
Kaufman Stephen C.
McGuireWoods LLP
Teska Kevin J.
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