Incremental critical area computation for VLSI yield prediction

Details Incremental critical area computation for VLSI yield prediction Incremental critical area computation for VLSI yield prediction

1998-04-30

2000-03-28

Teska, Kevin J.

3955002, G06F 1750

Patent

active

060442085

ABSTRACT:
An efficient method to compute critical area for shorts and breaks in rectilinear layouts in Very Large Scale Integrated (VLSI) circuits. The method is incremental and works in the L.sub..infin. geometry and has three major steps: Compute critical area for rectilinear layouts for both extra material and missing material defects (i.e., shorts and opens) by modeling defects as squares (which corresponds to the L.sub..infin. metric) instead of circles (Euclidean geometry). Treat the critical region for shorts and opens between any two edges or corners of the layout as a rectangle that grows uniformly as the defect radius increases. This is valid for rectilinear layouts and square defects (L.sub..infin. metric) . Use an incremental critical area algorithm for shorts and opens, which are computed for rectilinear layouts assuming square defects. Non-rectilinear layouts are approximated, first, by a rectilinear layout using a shape processing tool. The critical area for the rectilinear approximation is computed using the preferred incremental method.

REFERENCES:
patent: 3751647 (1973-08-01), Maeder et al.
patent: 5438527 (1995-08-01), Feldbaumer et al.
patent: 5544256 (1996-08-01), Brecher et al.
patent: 5649169 (1997-07-01), Berezin et al.
patent: 5754432 (1998-05-01), Komatsuzaki et al.
patent: 5773315 (1998-06-01), Jarvis
patent: 5777901 (1998-06-01), Berezin et al.
patent: 5841893 (1998-11-01), Ishikawa et al.
Wagner and Koren "An Interactive VLSI CAD Tool for Yield Estimation," IEEE Transactions on Semiconductor Manufacturing, vol. 8, No. 2, May 1995, pp. 130-138.
Allan and Walton "Efficient Critical Area Estimation for Arbitrary Defect Shapes," Proceedings of the 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 20-22, 1997, pp. 20-28.
Stapper and Rosner "Integrated Circuit Yield Management and Yield Analysis: Development and Implementation," IEEE Transactions on Semiconductor Manufacturing, vol. 8, No. 2 May 1995, pp. 95-102.

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