Incremental compilation of electronic design for work group

Details Incremental compilation of electronic design for work group Incremental compilation of electronic design for work group

1999-08-26

2001-10-02

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

Of instruction

C703S027000, C709S215000, C716S030000, C717S152000

Reexamination Certificate

active

06298319

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of electronic design automation. More specifically, the present invention relates to a technique for allowing multiple engineers to collaborate on one design project.
BACKGROUND OF THE INVENTION
In the field of electronics, various electronic design automation (EDA) tools are useful for automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs), and in the design of an integrated circuit that may be programmable. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). Programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), and a wide variety of other logic and memory devices that may be programmed. Often, such PLDs are designed and programmed by an engineer using an electronic design automation tool that takes the form of a software package.
The use of such a software package in programming a PLD allows an engineer to plan a design for the PLD, iterate over modifications to the design, test the design, and finally program the design into the PLD. In the past, one engineer was more than capable of designing and implementing the logic for one PLD. In other words, the capacity and complexity of past PLDs was not so much as to overwhelm one engineer because the PLDs were smaller in terms of the total logic elements they contained. Currently, however, PLDs are becoming larger, more complex, and include such powerful processing capabilities that it is becoming increasingly difficult for only one engineer to plan and implement a design for one PLD. For example, it is becoming extremely difficult for one engineer to develop a design for a PLD that includes around 100,000 logic elements or more, especially in the face of a tight schedule driven by time-to-market requirements. The short development time of a PLD is one of the strong reasons for choosing such a programmable device over other types of integrated circuits.
More frequently, integrated circuit customers who buy and program PLDs are choosing smaller devices because design entry can be performed by a single engineer in a reasonable amount of time. In such cases, only one engineer is needed to design and program each PLD. This approach has its drawbacks because the power of more complex PLDs is not being utilized. For those customers who choose to design a large circuit using a large, complex PLD, it is becoming increasingly difficult to coordinate the efforts of multiple engineers working on one design. The logistics of dividing up sections of the design to work on, keeping track of source files, and coordinating complied results amongst multiple engineers can be extremely difficult. Such coordination between multiple engineers working on a complex PLD design is becoming increasingly necessary as PLDs approach 100,000 logic elements and beyond. Without such coordination, the entire design process may take much longer than necessary and sub-optimal decisions may be made along the way.
Additionally, current compilers used with electronic design automation tools are often ill-suited for use by multiple engineers working on a complex PLD. When a minor change is made by one engineer to a small part of the overall PLD design, current compilers simply take all existing source files and recompile all of them in order to produce new compiled results. Once the complete design has been recompiled, it is then necessary to retest the complete design. Testing a complete design, including using a timing analyzer, simulation and creating vectors, can be very difficult and time consuming. During this time, the design must be frozen, thus preventing other engineers in the team from making and testing their own modifications.
Therefore, it would be desirable to have a technique for use with electronic design automation tools that allows multiple engineers to work in an efficient and coordinated fashion upon an electronic design for a complex integrated circuit, a multi-chip module, a circuit board, an ASIC, a PLD, etc. It would further be desirable for such an electronic design automation tool to have a compiler that was able to incrementally compile only those changes made by a single engineer so that the complete design would not have to be retested upon every compile.
SUMMARY OF THE INVENTION
To achieve the foregoing, and in accordance with the purpose of the present invention, a technique and system are disclosed that allow multiple engineers to collaborate in a work group on an electronic design, such as on a complex integrated circuit, a multi-chip module, a circuit board, an ASIC, a programmable logic device, etc. Such “work group computing” facilitates cooperation and sharing of information among multiple engineers so they can effectively and coherently work together on a complex design project. Engineers share project design files, assignment information, and processing operation results. This cooperation is especially advantageous for programmable logic devices that approach 100,000 logic elements and beyond.
In one embodiment of the invention, the system controls editing of files so that two engineers may not inadvertently edit the same global source file at the same time. The system also allows individual engineers to receive automatic updates of new versions of source files, allows files that are being edited to be locked, and provides for an isolation mode should an engineer wish to work with source files in an unchanging state. Advantageously, instead of a complex PLD design being broken up into multiple, smaller PLDs that are assigned to one engineer each, multiple engineers can efficiently work on a very complex design that can be implemented on a single, large capacity PLD. Each engineer is allowed to work on a portion of the overall design. Thus, designs of large PLDs can be completed faster and more efficiently. Additionally, the design of a complex PLD need not be broken up into various smaller, less complex PLDs which would result in an inefficient use of space on a circuit board.
In another embodiment of the invention, each engineer may incrementally compile local changes made to source files in his or her own user work space to produce a local set of compilation and processing results. The “basis” for incremental compilation is stored in the global work space. An engineer may thus make minor changes to one source file and incrementally compile only those changes using the basis from the global work space. Benefits of incremental compilation include a much faster compilation. Additionally, existing portions of the design not subject to recompilation may not need to be changed. For example, if the pinouts for a design have already been specified, and this portion is not subject to recompilation in an incremental compile, the pinouts will remain the same. Keeping large portions of the design static while only incrementally compiling smaller portions is advantageous in that those static portions do not have to be redesigned.
In one specific embodiment of the invention, incremental compilation includes the steps of: delineating a sphere of influence of user changes in a previously compiled design (the sphere of influence typically being defined within a netlist); and recompiling the logic from within this sphere of influence into appropriate logic elements available within a target hardware device. Such incremental compilation allows multiple engineers to share a single project and reduces compilation time for large devices.


REFERENCES:
patent: 3617714 (1971-11-01), Kernighan et al.
patent: 4827427 (1989-05-01), Hyduke
patent: 4882690 (1989-11-01), Shinsha et al.
patent: 5051938 (1991-0

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