Incremental bus reconfiguration without bus resets

Details Incremental bus reconfiguration without bus resets Incremental bus reconfiguration without bus resets

1998-11-06

1999-08-10

Donaghue, Larry D.

Electrical computers and digital processing systems: multicomput

Network computer configuring

Reconfiguring

710 10, 710104, G06F 1300

Patent

active

059352086

ABSTRACT:
An electronic system interconnect. The interconnect comprises a first node and a second node coupled to the first node. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect is initially configured, and the first node responds to the addition of the third node by initiating a new connect handshake with the third node. The first node begins by transmitting a first signal to the third node. The first node signals that the third node has been added to the interconnect if the third node responds to the first signal by transmitting a second signal. The first node causes the interconnect to be reconfigured if the third node transmits a third signal in response to receiving the first signal.

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