Incremental automata verification

Details Incremental automata verification Incremental automata verification

2005-10-18

2005-10-18

Paladini, Albert W. (Department: 2125)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C714S039000

Reexamination Certificate

active

06957178

ABSTRACT:
Methods and apparatus for performing formal verification of a system defined by a set of automata are useful in facilitating computing efficiencies during the verification of an incremental system design. The various embodiments permit computing efficiencies by saving information generated during a verification of the system for use in subsequent verification runs. The saved information includes calculation results pertaining to instances or elements of the system that do not require modification for the next subsequent verification.

REFERENCES:
patent: 4571072 (1986-02-01), Bourbeau, Jr. et al.
patent: 4711024 (1987-12-01), Russell
patent: 4894829 (1990-01-01), Monie et al.
patent: 5163016 (1992-11-01), Har'El et al.
patent: 5291427 (1994-03-01), Loyer et al.
patent: 5483470 (1996-01-01), Alur et al.
patent: 5491639 (1996-02-01), Filkorn
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5691925 (1997-11-01), Hardin et al.
patent: 5815717 (1998-09-01), Stack
patent: 5828812 (1998-10-01), Khan et al.
patent: 5937190 (1999-08-01), Gregory et al.
patent: 5966516 (1999-10-01), De Palma et al.
patent: 6059837 (2000-05-01), Kukula et al.
patent: 6077305 (2000-06-01), Cheng et al.
patent: 6102958 (2000-08-01), Meystel et al.
patent: 6102959 (2000-08-01), Hardin et al.
patent: 6110218 (2000-08-01), Jennings
patent: 6132109 (2000-10-01), Gregory et al.
patent: 6141633 (2000-10-01), Iwashita et al.
patent: 6499132 (2002-12-01), Morley et al.
patent: 6526544 (2003-02-01), Peled et al.
R. Alur and D. Dill, “Automata-theoretic Verification of Real-Time Systems”, Nov. 2, 1995, pp. 1-27.
M. Archer and C. Heirmeyer, “Mechanical Verification of Timed Automata: A Case Study”, 1996, pp. 1-12.
R. Goering, “Design Automation: Breakthrough claimed in functional verification”, EE Times, May 21, 2001, pp. 59-62.
F. Laroussinie et al., “From Timed Automata to Logic—and Back”, BRICS—Jan. 1995, 22 pgs.
N. Lynch and F. Vaandrager, “Forward and Backward Simulations Part II: Timing-Based Systems”, Apr. 26, 1995, pp. 1-49.
B. Plateau and W. Stewart, “Stochastic Automata Networks: Product Forms and Iterative Solutions”, INRIA—1996, pp. 1-38.

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