Semiconductor device manufacturing: process – Voltage variable capacitance device manufacture
Reexamination Certificate
2003-06-04
2004-11-30
Flynn, Nathan J. (Department: 2826)
Semiconductor device manufacturing: process
Voltage variable capacitance device manufacture
C257S312000, C257S595000, C257S596000, C257S599000, C257S600000
Reexamination Certificate
active
06825089
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a varactor design and, more specifically, a high quality large capacitance varactor having an increased ratio of capacitance to area for the varactor and a method of manufacture thereof.
BACKGROUND OF THE INVENTION
Portable telecommunications applications place stringent requirements on the design of oscillators, such as voltage-controlled oscillators, in transceivers. The oscillator should have a large tuning range with minimal noise, low power dissipation, low manufacturing cost, and limited susceptibility to crosstalk from other circuits.
The design of varactors, also known as a voltage variable capacitors, is an important aspect of optimizing such oscillators. Both P/N junction semiconductor and metal oxide semiconductor (MOS) capacitors are commonly used. Semiconductor varactor designs are subject to three general considerations; (1) maximize capacitance per unit area occupied by the varactor, (2) maximize the voltage controllable variable capacitance range of the varactor, and (3) maximize the quality factor (Q) of the varactor. Designing and manufacturing semiconductor varactors in which all three considerations have been optimized remains problematic.
For example, certain MOS varactors, may use low doped wells biased with respect to a conductive layer, such as a MOS-type gate, to vary the gate-controlled capacitance in a channel region of the well below the gate. The low doping density of the well, however, has a high series resistance, which in turn degrades the Q of the varactor. Alternatively, the use of a heavily doped channel, while minimizing series resistance may also substantially eliminate voltage controllable variable capacitance.
Previous attempts to resolve this problem have focused on reducing the device dimensions, allowing large perimeters with highly conductive contacts. Such attempts, however, result in devices having a large area to capacitance ratio. Moreover the device has substantial substrate pickup due to the large device area overlapping with the substrate.
Others have attempted to increase the total variable capacitance of P/N junction semiconductor capacitors by implanting P+ into a N-epitaxial layer. Such capacitors are expected, however, to have a small capacitance variation with voltage bias as they implement a pn junction. Increasing their quality factor requires an extra processing step, the growth of a of heavily doped buried layer, that is not commensurate with the CMOS process.
Accordingly, what is needed in the art is a semiconductor varactor with a high capacitance per unit area, high variable capacitance and high quality factor.
SUMMARY OF THE INVENTION
A new semiconductor varactor design is presented to address the above-discussed deficiencies of the prior art. In one embodiment of the present invention, the semiconductor varactor comprises a semiconductor substrate of a first conductivity type and a well of a second conductivity type in the semiconductor substrate. The semiconductor varactor further comprises a conductive layer over the well and a conductive region in the well. The conductive region has a same conductivity type as the well but with a lower resistivity than the well and at least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of the conductive layer.
In another embodiment, the present invention provides a method of manufacturing a semiconductor varactor. The method comprises providing a semiconductor substrate of a first conductivity type, forming a well and locating a conductive region in the semiconductor substrate. The conductive region has the same conductivity type as the well but with a lower resistivity than the well. The method further includes forming a conductive layer over the well such that at least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of the conductive layer.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the scope of the invention.
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Johnson Debra
Moinian Shahriar
Shapira Shye
Agere Systems Inc.
Flynn Nathan J.
Forde Remmon R.
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