Increased lock range PLL for constrained data

Details Increased lock range PLL for constrained data Increased lock range PLL for constrained data

2000-03-03

2002-12-10

Hudspeth, David (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

C360S046000

Reexamination Certificate

active

06493163

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to the field of disk drive systems, and in particular to a disk drive system with increased reliability resulting from an increased lock range in an I.T.R. circuit.
2. Statement of the Problem
FIG. 1
shows a disk drive system
100
. The disk drive system
100
includes a disk device
102
connected to control circuitry
106
. The disk device
102
includes storage media
104
that stores data. Some examples of the storage media
104
are magnetic and optical disks. The control circuitry
106
includes a read channel circuit
120
that processes signals from the disk device
102
to re-produce the stored data. The read channel circuit
120
includes a sampling circuit
122
, an adaptive filter
124
, an interpolated timing recovery (I.T.R.) circuit
126
, a detector
128
, and a decoder
130
all connected in series. The I.T.R. circuit
126
includes an interpolator
142
that is connected to the adaptive filter
124
and the detector
128
. The I.T.R. circuit
126
also includes a phase error detector
144
, a filter
146
, and an accumulator
148
that are connected in series to form a phase lock loop
140
for the interpolator
142
.
If the storage media
104
is a magnetic disk, then the data is exchanged with the magnetic disk as follows. A signal representing the data drives a magnetic head. The magnetic head alters a magnetic field to create magnetic transitions on the magnetic disk. These magnetic transitions represent the data. The head subsequently detects the magnetic transitions to generate a read signal
110
. The read signal
110
represents the magnetic transitions. The read channel circuit
120
processes the read signal
110
to produce a data signal
131
that represents the data.
If the storage media
104
is an optical disk, then the data is exchanged with the optical disk as follows. A signal representing the data drives a device that creates pits in the surface of the optical disk. The pits create physical transitions that represent the data. An optical pick-up projects a laser onto the surface of the disk and detects the reflection to generate the read signal
110
. The read signal
110
represents the physical transitions. The read channel circuit
120
processes the read signal
110
to produce a data signal
131
that represents the data.
To read the data, the magnetic head or optical pick-up must first be positioned over the transitions on the disk that correspond to the data. To facilitate this positioning, servo information that identifies various locations on the disk is stored on the disk at the corresponding locations. The read signal includes this servo information. The control circuitry
106
processes the servo information to control the positioning of the disk device
102
.
The read channel circuit
120
operates as follows to convert the read signal
110
into the data signal
131
. The sampling circuit
122
converts the read signal
110
from analog to digital by sampling the read signal
110
to generate read samples
123
for the adaptive filter
124
. The adaptive filter
124
removes distortion by shaping the read samples
123
to generate equalized samples
125
for the I.T.R. circuit
126
. The I.T.R. circuit
126
synchronizes the equalized samples
125
with the detector
128
clock by interpolating the equalized samples
125
at the detector
128
clock times to generate interpolated samples
127
. The detector
128
converts the interpolated samples
127
into an encoded bit stream
129
by processing the interpolated samples
127
with a detection algorithm, such as a Viterbi state machine. The decoder
130
decodes the encoded bit stream
129
into the data signal
131
by applying a decoding technique, such as PR4 with D=1 constraints.
The I.T.R. circuit
126
operates as follows to synchronize the equalized samples
125
with the detector
128
clock. The interpolator
142
receives the equalized samples
125
from the adaptive filter
124
. The interpolator
142
synchronizes the equalized samples
125
with the detector
128
clock by interpolating the equalized samples
125
at the detector
128
clock times to generate interpolated samples
127
. In the phase lock loop
140
, the phase error detector
144
receives the interpolated samples
127
and determines the phase error between the interpolated samples
127
and the detector
128
clock. The phase error detector
144
generates and transfers phase error data
145
to the filter
146
. The filter
146
receives and filters the phase error data
145
to stabilize the phase lock loop
140
. The filter
146
transfers the filtered phase error data
147
to the accumulator
148
. The accumulator
148
receives and accumulates the filtered phase error data
147
. The accumulator
148
transfers the accumulated phase error data
149
to the interpolator
142
. The interpolator
142
uses the accumulated phase error data
149
from the phase lock loop
140
to more accurately synchronize the equalized samples
125
with the detector
128
clock. The I.T.R. circuit
126
configuration is a conventional phase lock loop
140
that is well known in the art. The interpolator
142
, the filter
146
, and the accumulator
148
are conventional components and for a more detailed description, refer to U.S. Pat. No. 5,909,332 entitled “Sampled Amplitude Read Channel Employing Interpolated Timing Recovery”, which is hereby incorporated by reference into this application.
FIG. 2
depicts the phase error detector
144
within the I.T.R. circuit
126
. The phase error detector
144
includes a first delay
210
, a second delay
211
, a slicer
220
, a first multiplier
230
, a second multiplier
231
, and a subtractor
240
. The phase error detector
144
generates phase error data
145
for the phase lock loop
140
. The phase error data
145
allows the I.T.R. circuit
126
to more accurately synchronize the equalized samples
125
with the detector
128
clock.
The slicer
220
generates a binary output by comparing the input sample to a positive and,negative threshold. If the sample is above the positive threshold, then the output is a “1”. If the sample is below the negative threshold, then the output is a “−1”. If the sample is between the positive and negative thresholds, then the output is a “0”.
The phase error detector
144
receives the interpolated samples
127
from the interpolator
142
including a current sample y
0
and a previous sample y
1
. The slicer
220
slices the current sample y
0
to generate a current slice value s
0
. The first multiplier
230
receives and multiplies the current slice value s
0
and the previous sample y
1
to generate a first result s
0
y
1
. The first delay
210
stores the previous sample y
1
for the first multiplier
230
. The first multiplier
230
transfers the first result s
0
y
1
. The second multiplier
231
receives and multiplies the current sample y
0
and a previous slice value s
1
to generate a second result s
1
y
0
. The previous slice value s
1
is the result of the slicer
220
slicing the previous sample y
1
as described above. The second delay
211
stores the previous slice value s
1
for the second multiplier
231
. The second multiplier
231
transfers the second result s
1
y
0
. The subtractor
240
receives the first result s
0
y
1
and the second result s
1
y
0
, and subtracts the second result s
1
y
0
from the first result s
0
y
1
to generate a final result s
0
y
1
−s
1
y
0
. The final result s
0
y
1
−s
1
y
0
represents the phase error corresponding with the current sample y
0
. The phase error detector
144
transfers the final result s
0
y
1
−s
1
y
0
as the phase error data
145
.
The performance of the phase lock loop
140
is characterized by a lock range. The lock range indicates the amount of phase error that can be corrected by the phase lock loop
140
. When the phase error exceeds the lock range, the phase lock loop
140
operates as if there is no phase error. This results in a false lock w

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