Increased functionality for Holladay halftoning

Details Increased functionality for Holladay halftoning Increased functionality for Holladay halftoning

1998-01-07

2001-03-27

Lee, Thomas D. (Department: 2724)

Facsimile and static presentation processing

Static presentation processing

Attribute control

C382S237000

Reexamination Certificate

active

06208430

ABSTRACT:

BACKGROUND OF THE INVENTION
A circuit for storing low addressability halftone arrays for a high addressability printer in a reduced amount of memory by storing high addressability arrays at one location per sub pixel, and low addressability pixels at one location per pixel, and by arranging the halftone generator to output each low addressability pixel a number of times to match the number of sub pixels per pixel.
In a regular printer, halftone arrays are stored at one location per pixel. As each pixel is received, it is compared to the array output and then output as either a ONE or a ZERO, depending on the comparison. Then the next array value is compared to the next pixel, etc.
In a high addressability printer, each pixel is divided up into a number of sub pixels, and there is an array location for each. For a numerical example, assume an addressability factor of 4. Then each pixel will be divided up into 4 sub pixels, and four comparisons will be used to generate 4 sub pixels to be printed. The result is that the regular 4 by 4 array must now be 16 by 4, and more memory is needed.
A problem arises when large numbers of large dots, such as 128 by 128 pixels, are needed, in which case the amount of memory for the storage of all the arrays becomes excessive. A method of reducing the storage requirement is needed.
SUMMARY OF THE INVENTION
In this case some dots, such as clustered dots, can be stored as high addressability dots, and others, such as stochastic dots, can be stored as regular dots. For example, to continue the numerical example, there can be 16 by 4 high addressability dots, and 4 by 4 low addressability dots, the latter having a much reduced memory requirement. If this is true, there must be a change made to the system. In its most useful form, the original page description language which specifies the original images also contains a “hint” which specifies the halftone dot and its addressability. As the image goes through the page generation process, the hint is carried along and finally is applied to the halftone generator, where it is used to select the correct dot, and also is used to select the corresponding addressability.
The printer does not have a variable clock speed, assuming full time high addressability. However, the array circuit can be enabled to either output 4 threshold values for 4 clocks, or the same output value 4 times for 4 clocks. Thus, the low addressability arrays can be stored as regular arrays, in ¼ the amount of memory.


REFERENCES:
patent: 4706077 (1987-11-01), Roberts et al.
patent: 4734787 (1988-03-01), Hayashi
patent: 4920501 (1990-04-01), Sullivan et al.
patent: 5019896 (1991-05-01), Shimazaki
patent: 5642439 (1997-06-01), Sato et al.
patent: 5940138 (1999-08-01), Lowe

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