In-system programming architecture for a multiple chip processor

Details In-system programming architecture for a multiple chip processor In-system programming architecture for a multiple chip processor

1995-05-19

1996-10-15

Shah, Alpesh M.

Boots, shoes, and leggings

3642328, 3642327, 3642323, 3642384, 364DIG1, G06F 1576

Patent

active

055663443

ABSTRACT:
An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.
The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die. The address and program data are then parallel output from separate registers on the memory die along with a program pulse to program the memory core.

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Mano, Morris, "Computer Engineering: Hardware Design" pp. 286-292, 1991.

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