In-situ test and diagnostic circuitry and method for CML chips

Registers – Systems controlled by data bearing records – Time analysis

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324 73R, G01R 3128, G06F 1100

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041834607

ABSTRACT:
An In-Situ Test and Diagnostic Circuit and Method to monitor the integrity of external connections of a current mode logic integrated circuit chip (inputs and outputs) as well as the integrity of the logic function thereof. The circuit comprises three parts: an "Open" Input Detector to detect open connections or connections that are becoming open between one chip and another; an Output Short Detector to monitor shorts at any chip output; and a Signature Test and Diagnostic circuit to determine if the logic function of the chip itself is operational. All the foregoing circuit parts are formed as an integral part of each CML chip and connected to an output terminal called a Test and Diagnostic Pin.

REFERENCES:
patent: 3582633 (1971-06-01), Webb
patent: 3739160 (1973-06-01), El-Hasan et al.
patent: 3815025 (1974-07-01), Jordan
patent: 3919533 (1975-11-01), Einolf, Jr., et al.
patent: 3924181 (1975-12-01), Alderson
patent: 3976864 (1976-08-01), Gordon
patent: 4074189 (1978-03-01), Harms et al.
Barnard & McMahon, Shift Register Tester on a Chip, IBM Technical Disclosure Bulletin, vol. 15, No. 9, Feb. 1973, pp. 2935-2936.
Leininger, On--Chip Testing Enhancement of a Single--Chip Microprocessor, _IBM Technical Disclosure Bulletin, vol. 21, No. 1, Jun. 1978, pp. 5-6.

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