In-situ P doped amorphous silicon by NH3 to form oxidation resis

Details In-situ P doped amorphous silicon by NH3 to form oxidation resis In-situ P doped amorphous silicon by NH3 to form oxidation resis

1997-12-18

2000-10-31

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438714, 438743, H01L 21302

Patent

active

06140246&

ABSTRACT:
A polysilicon-based floating gate is formed so as to be resistant to oxidation that occurs during multiple thermo-cycles in fabrication. Accordingly, edge erase times in NOR-type memory devices may be minimized. Additionally, manufacture of oxidation resistant floating gates reduces variations in edge erase times among multiple NOR-type memory devices. A layer of amorphous silicon is deposited on a silicon substrate by directing silane, a phosphene and helium gas mixture, and ammonia at the surface of the silicon substrate thereby doping the amorphous silicon in situ. The amorphous silicon layer is then etched so as to overlap slightly with regions that will later correspond to the source and drain regions. Next, a lower oxide layer of an ONO dielectric is deposited and the device is heated. A thermo-cycle is eliminated by heating the amorphous silicon during formation of the oxide layer rather than immediately following its deposition. Later, the nitride and oxide layers of the ONO dielectric, a second polysilicon layer, a tungsten silicide layer, and SiON layers are successively formed.

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U.S. Patent Application, Serial No. 08/993,443; Filed: Dec. 18, 1997; Entitled: Nitrogen Ion Implanted Amorphous Silicon to Produce Oxidation Resistant And Finer Grain Polysilicon Based Floating Gates; Inventors: Kent K. Chang, et al.; attorney docket No. M-5386 US.

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