In-situ nano-interconnected circuit devices and method for...

Semiconductor device manufacturing: process – Having superconductive component

Reexamination Certificate

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C438S618000, C438S962000

Reexamination Certificate

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06297063

ABSTRACT:

RELATED APPLICATIONS
This application is related to U.S. patent application Ser. No. 09/405,691, titled “Tactile Sensor Comprising Nanawires and Methodfor Making the Same,” filed Sep. 24, 1999, by inventor Jin herein, and U.S. Pat. application Ser. No. 09/420,157, titled “Article Comprising Vertically Nano-Interconnected Circuit Devices and Method for Making the Same,” filed concomitantly herewith, by inventors Brown, Jin and Zhu herein, both of which are assigned to the present assignee and incorporated herein by reference.
FIELD OF THE INVENTION
This invention relates to structures for nano-interconnected circuits and methods of making same, and more particularly, to structures interconnected with conductive nanowires and methods for making the interconnections in-situ.
BACKGROUND OF THE INVENTION
Nano-scale wires such as carbon nanotubes with a very small size scale, on the order of 1-100 nanometers in diameter and 0.1-100 &mgr;m in length, have received considerable attention in recent years. See Liu et al., SCIENCE, Vol. 280, p. 1253 (1998); Ren et al., SCIENCE, Vol. 282, p. 1105 (1998); Li et al., SCIENCE, Vol. 274, p. 1701 (1996); Frank etal., SCIENCE, Vol. 280, p. 1744 (1998); J. Tans et al., NATURE, Vol. 36, p. 474 (1997); Fan et al., SCIENCE, Vol. 283, p. 512 (1999); Collins et al., SCIENCE, Vol. 278, p. 100 (1997); Kong et al., NATURE, Vol. 395, p. 878 (1998); and Ebbesen et al., NATURE, Vol. 382, p. 54 (1996).
Carbon nanotubes exhibit unique atomic arrangements, nano-scale structures and interesting physical properties such as one-dimensional electrical behavior, quantum conductance, and ballistic transport characteristics. The ballistic transport in carbon nanotubes, as reported by Frank et al, allows the passage of huge electrical currents in electronic circuits, with the magnitude of current density comparable to or better than those in some superconductors. Carbon nanotubes are one of the smallest dimensioned nanowire materials with generally high aspect ratio. They may have a small diameter of ~1 nm in the case of single-wall nanotubes and less than ~50 nm in the case of multi-wall nanotubes. See Rinzier et al, APPLIED PHYSICS, Vol. A67, p. 29 (1998); Kiang et al, J. PHYSICAL CHEM., Vol. 98, p. 6612 (1994), and Kiang et al, PHYSICAL REVIEW LETTERS, Vol, 81, p. 1869 (1998).
High-quality single-walled carbon nanotubes are typically grown as randomly oriented, needle-like or spaghetti-like, tangled nanotubes by laser ablation or arc techniques (a chemical purification process is usually needed for arc-generated carbon nanotubes to remove non-nanotube materials such as graphitic or amorphous phase, catalyst metals, etc.). Chemical vapor deposition (CVD) methods such as used by Ren et al., Fan et al., and Li et al tend to produce multiwall nanotubes attached to a substrate, often with a semi-aligned or an aligned, parallel growth perpendicular to the substrate. As described in these artides, catalytic decomposition of hydrocarbon-containing precursors such as ethylene, methane, or benzene produces carbon nanotubes when the reaction parameters such as temperature, time, precursor concentration, flow rate, are optimized. Nucleation layers such as a thin coating of Ni, Co, Fe, etc. are often intentionally added to the substrate surface to nucleate a multiplicity of isolated nanotubes. Carbon nanotubes can also be nucleated and grown on a substrate without using such a metal nucleating layer, e.g., by using a hydrocarbon-containing precursor mixed with a chemical component (such as ferrocene) which contains one or more of these catalytic metal atoms. During the chemical vapor decomposition, these metal atoms serve to nucleate the nanotubes on the substrate surface. See Cheng et al., CHEM. PHYSICS LETTERS, Vol. 289, p. 602 (1998).
The modern trend in electronic circuit design, interconnection and packaging is toward use of finer features, such that submicron feature sizes have been reached in recent years. To produce desired, ultra-high density electronic packaging, a small width of the circuit lines is important, as well as a three-dimensional, multi-layer configuration with vertically-integrated circuit layers. However, nanowires grown with presently-available methods are not suitable for such purposes. The as-grown single-wall nanotubes (SWNT) such as commonly synthesized by laser ablation or arc method, have a spaghetti-like configuration and often are tangled with each other. The multi-wall nanotubes (MWNT), such as commonly made by chemical vapor deposition, are easier to prepare in an aligned and parallel configuration. However, these as-grown nanotubes such as reported by Ren et al. and Li, et al. differ in height or length. For reliable circuit interconnections without electrical shorts or opens, it is desirable to prepare nanowires having equal and specific predetermined lengths. Co-pending application titled “Article Comprising Vertically Nano-Interconnected Circuit Devices and Methodfor Making the Same,” filed concomitantly herewith by inventors Brown, Choi and Jin herein, discloses fabrication approaches for equalizing the length of nanowires and bonding them to circuit substrates for interconnections. However, it also would be advantageous to provide a method for growing the nanowires in-situ between circuit pads or components thereby avoiding equalization and soldering operations.
SUMMARY OF THE INVENTION
The invention comprises a nano-interconnected circuit device having at least two circuit layers or circuit devices which are placed either in a parallel configuration or in a side-by-side configuration, and a plurality of substantially equi-length nanowires disposed therebetween. Also disclosed is a method of making the devices comprising in-situ growth of the nanowires on at least one of the circuit substrates of the interconnected device. The method of in situ growth comprises providing at least a first and a second circuit substrate; aligning the circuit substrates in a spaced-apart substantially parallel relation to define a gap therebetween; depositing a catalytic nucleation layer on at least one of the circuit substrates; and growing a plurality of nanowires from the catalytic nucleation layer so that the plurality of nanowires are disposed between the first and second substrates. The as-grown nanowires are connected to provide the interconnected circuit device. In one embodiment, the nanowires are grown from both the first and second substrates and are connected by being merged as they grow together. In another embodiment, the nanowires are grown from one of the circuit substrates and then solder bonded to the other circuit substrate. In yet another embodiment, the nanowires are grown so that adjacent nanowires will overlap when the first and second circuit substrates are aligned, and then the adjacent nanowires are interconnected with Van der Waals attraction bonding and optional further electrical connections. With this invention, vertical or horizontal interconnections can be achieved.


REFERENCES:
Nassiopoulou, A. G.; “Low Dimensional Silicon for Integrated Optoelectronics”; Semiconductor Conference, 1998; Oct. 6-10, 1998; pp. 417-426.*
Fujita et al. “A Micromachined Tunneling Current Device for the Direct Observation of the Tunneling Gap”; Emerging Technologies and Factory Automation, 1999; Oct. 18-21, 1999; pp. 367-372.*
Fan et al., “Self-Oriented Regular Arrays of Carbon Nanotubes and Their Field Emission Properties”, Jan. 22, 1999, vol. 283 Science, pp. 512-514.
Kong et al., “Synthesis of Individual Single-Walled Carbon Nanotubes on Patterned Silicon Wafers”, vol. 395, Oct. 29, 1998, pp. 878-881.
Li et al., “Large-Scale Synthesis of Aligned Carbon Nanotubes”, vol. 274, Dec. 6, 1996, pp. 1701-1703.
Ren et al., “Synthesis of Large Arrays of Well-Aligned Carbon Nanotubes on Glass”, vol. 282, Nov. 6, 1998, Science, pp. 1105-1107.

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