In-situ liner for isolation trench side walls and method

Details In-situ liner for isolation trench side walls and method In-situ liner for isolation trench side walls and method

2000-05-11

2001-10-23

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S427000

Reexamination Certificate

active

06306725

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of semiconductor devices, and more particularly to an in-situ liner for isolation trench side walls and to a method of forming the same.
BACKGROUND OF THE INVENTION
Semiconductor components must be properly isolated from one another to function properly. For example, the state and conductance of individual transistors can only be controlled if proper isolation exists among the transistors. If not, leakage currents may occur, causing power dissipation, noise-margin degradation, and voltage shift on dynamic nodes. Additionally, cross talk among transistors can destroy the logic state of a gate.
In the past, field oxide bumps (LOCOS) have been used to isolate components of an integrated circuit. Field oxide bumps are typically formed by first pattern and etching the isolation areas. The substrate is then subjected to thermal treatment to grow field oxide at the isolation areas. Field oxide bumps are not scalable below 0.5 microns. Accordingly, field oxide bumps do not provide a satisfactory isolation system for sub 0.5 micron applications.
More recently, shallow trench isolation structures have been used for sub 0.5 micron applications. Typically, a narrow trench is formed in a substrate. The trench may be filled with an insulating material using high density plasma deposition to prevent voids from forming in the insulating material of the trench. High density plasma deposition results in a high density oxide that advantageously resists etching and other processing steps associated with semiconductor fabrication. Such shallow trench isolation structures, however, often leak current, which degrades integrated circuit performance.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen in the art for an improved integrated circuit isolation structure. The present invention provides an isolation structure that substantially eliminates or reduces the disadvantages and problems associated with using high density plasma (HDP) chemical vapor deposition (CVD) to form shallow trench isolation structures.
In accordance with the present invention, an isolation trench may comprise a trench formed in a semiconductor layer. A barrier layer may be formed along the trench. A layer of an insulating material may be formed over the barrier layer. A high density layer of the insulating material may be formed in the trench over the layer.
More specifically, in accordance with one embodiment of the present invention, the barrier layer may comprise a thermal oxide. The layer of the insulation material may comprise a thermally treated low density oxide. The low density oxide may be an oxide deposited using high density plasma deposition with a low bias RF. The high density layer of the insulation material may comprise an oxide deposited using high density plasma deposition with a high bias RF.
Important technical advantages of the present invention include providing a shallow trench isolation structure that substantially reduces or eliminates current leakage. In particular, a layer of low density oxide may be first deposited in an isolation trench. The layer prevents sputtering associated with later high density plasma deposition from damaging the trench side walls and causing current leakage.
Another technical advantage of the present invention includes providing a robust trench oxide. In particular, the layer of low density oxide may be densified by thermal treatment.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.


REFERENCES:
patent: 4952524 (1990-08-01), Lee et al.
patent: 5420065 (1995-05-01), Philipossian
patent: 5492858 (1996-02-01), Bose et al.
patent: 5719085 (1998-02-01), Moon et al.
patent: 5851899 (1998-12-01), Weigand
patent: 6033970 (2000-03-01), Park
patent: 6071792 (2000-06-01), Kim et al.

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