Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
1999-05-17
2001-03-06
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S663000
Reexamination Certificate
active
06198294
ABSTRACT:
BACKGROUND
The present invention concerns processing of integrated circuits and pertains particularly to in-situ monitoring of wafer thickness during backgrinding.
Before dividing silicon wafers into dies and packaging the resulting integrated circuits, it is often necessary to grind the back of a wafer until the wafer is a predetermined thickness. Such wafer backgrind processes control grind thickness using a feedback loop where wafer thickness is measured at the center of the product wafer. The center wafer measurement is used for feedback. Test wafers or product wafers are used to monitor thickness and thickness range of the grind process. Test wafers are used to initially verify the thickness range of the grind process after maintenance, a change in grind thickness or other change in the grind process. The feedback uses the thickness of an already ground product wafer to provide feedback during grinding a new product wafer. However, there are several deficiencies in this system.
For example, it is impossible to monitor uniformity on product wafers without taking ex-situ (i.e., not during actual performance of grinding) measurements on a previously ground batch of product wafers. Generally, such monitoring requires a separate metrology tool and thickness measurement step. Also, a separate measurement stage on the grinder itself is required for checking the thickness of the wafer. Using this methodology, a certain lack of uniformity in wafer thickness can result. The lack of uniformity in wafer thickness can result in wafer bow and stress. Further, lack of grind uniformity can result in stresses in silicon and thin films placed on the wafer surface. These stresses can lead to cracks and voids in the silicon substrate. Also hillocks and film peeling can occur on the device side of the wafer if stresses in the wafer are not kept in check. Further, sometimes wafers break when grinder setup is not done properly. Additionally, the above-described methodology introduces a significant time lag between the actual grinding and the detecting of a lack of uniformity or improper thickness in a batch of wafers.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention thickness of a wafer is monitored during grinding. A conductive plate is located below the wafer during grinding. One or more capacitive sensors are located above the wafer during grinding. A monitoring device monitors capacitance of the conductive plate and the capacitive sensor.
For example, the conductive plate is embedded within a chuck onto which the wafer is placed during grinding. The capacitive sensors are mounted within a rod suspended over the wafer during grinding.
The present invention allows a user to monitor the grind process with real-time measurements and precisely define material removal and thus, process endpoint. In the preferred embodiment, capacitance is measured in several locations across the radius of the rotating wafer. The wafer is treated as a dielectric in this capacitive system. As the wafer thins capacitance decreases. The grind process is stopped automatically when the desired capacitance and corresponding wafer thickness is reached. The result is a repeatable endpoint and consistent post-grind thickness & uniformity, increased yield, and lower cost of ownership through improved tool efficiency and lower test wafer usage. The present invention also provides a diagnostic tool for users to monitor tool function over time.
The invention provides many advantages over prior art systems. For example, the present invention allows grind rate and wafer thickness to be monitored during polish. This allows technicians to quickly react to uniformity and thickness issues. The present invention makes possible grinding to a thickness endpoint since the capacitance at the final thickness can be taught. Also, wafer thickness uniformity can be monitored at the same time. Improved uniformity reduces wafer bow and stress.
Further, using the present invention, die yield and reliability are improved through better wafer thickness control in several ways. First, the control of grind uniformity reduces the stresses in the silicon and thin films on the wafer surface. These stresses can lead to cracks and voids in the silicon substrate. Also hillocks and film peeling can occur on the device side of the wafer if stresses in the wafer are not kept in check. Second, the die assembly yield increases when die thickness is controlled more tightly. This is important as packaging sizes continue to shrink. Third, process yield for the backgrind area is increased since many wafer break situations are related to grinder setup issues. The symptoms of these problems can be caught immediately with in-situ monitoring as provided by the present invention.
Further, the present invention allows for reduced production costs by increasing grind throughput. Throughput is increased because grinding is done only as long as needed. Also the incident angle of the grind wheel can be optimized and monitored for the most efficient grinding. The present invention allows thickness and uniformity to be monitored on product wafer. This eliminates the need for a separate metrology tool and thickness measurement step for monitoring grind performance. Also the separate measurement stage on the grinder itself that is used for checking the thickness of the wafer can be removed. The result is a smaller grinder footprint in backgrinders designed in accordance with the present invention. Another cost reduction is from reduction of test wafer usage for qualification. With the present invention, the need to use test wafers to monitor thickness and thickness range for the grind process is significantly reduced. For example, test wafers now need only be used for verifying operation after preventative maintenance or after another significant change in the tool set-up. Other uses of a test wafer are replaced by the capacitance monitoring of wafers.
Finally, the present invention allows a user to troubleshoot grinder performance. Data can be saved and logged for each wafer pass to provide both a history of each lot run and trend data for tool performance. For example, a wafer that breaks during grind would give a noisy signal easily recognized by the user.
REFERENCES:
patent: 4860229 (1989-08-01), Abbe et al.
patent: 4910453 (1990-03-01), Abbe et al.
patent: 5081421 (1992-01-01), Miller et al.
patent: 5337015 (1994-08-01), Lustig et al.
Brown Glenn W.
VLSI Technology Inc.
Weller Douglas L.
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