Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1998-12-07
2001-04-24
Morgan, Eileen P. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S285000, C451S287000, C451S056000, C451S443000
Reexamination Certificate
active
06220936
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the field of Chemical Mechanical Polishing (CMP). More particularly, the present invention relates to methods and apparatus for chemical mechanical polishing of substrates, such as semiconductor substrates, on a rotating polishing pad in the presence of chemically and/or physically abrasive slurry. The present invention provides a pad profile conditioning apparatus to condition the polishing pad while the polishing pad is being used to polish semiconductor substrates.
(2) Description of the Prior Art
Chemical Mechanical Polishing is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials therein, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
The use of chemical mechanical polishing to planarize semiconductor substrates has not met with universal acceptance, particularly where the process is used to remove high elevation features created during the fabrication of microelectronic circuitry on the substrate. One primary problem which has limited the used of chemical mechanical polishing in the semiconductor industry is the limited ability to predict, much less control, the rate and uniformity at which the process will remove material from the substrate. As a result, CMP is a labor intensive process because the thickness and uniformity of the substrate must be constantly monitored to prevent overpolishing or inconsistent polishing of the substrate surface.
The profile of the polishing pad plays an important role in determining good overall polishing results. The polishing pad can, for instance, be profiled thick at the inner diameter of the polishing pad as compared to the outer diameter of the polishing pad and visa versa. The profile of the polishing pad is typically achieved by trial and error and by adjusting the position of a diamond dresser (see following paragraph). This method of profiling the polishing pad is destructive, time consuming and causes the loss of the polishing pad. Since this measure of the polishing pad profile can only be performed at the end of the useful life of the polishing pad, the wrong profile can only be detected after the polishing pad has served its useful life.
The function of the diamond dresser is to maintain and/or restore the polishing characteristics of the polishing pad to the maximum extent possible during the polishing operation and in doing so to extend the useful life or the operating characteristics of the polishing pad. The diamond dresser performs this function by influencing the polishing action of the polishing pad during its operation. This influencing can take the form of exerting pressure on the polishing pad and in so doing influencing the polishing characteristics of the polishing pad.
The polishing process is carried out until the surface of the wafer is ground to a highly planar state. During the polishing process, both the wafer surface and the polishing pad become abraded. After numerous wafers have been polished, the polishing pad becomes worn to the point where the efficiency of the polishing process is diminished and the rate of removal of material from the wafer surface is significantly decreased. It is usually at this point that the polishing pad is treated and restored to its initial state so that a high rate of uniform polishing can once again be obtained.
FIG. 1
shows a Prior Art CMP apparatus. A polishing pad
20
is affixed to a circular polishing table
22
that rotates in a direction indicated by arrow
24
at a rate in the order of 1 to 100 RPM. A wafer carrier
26
is used to hold wafer
18
face down against the polishing pad
20
. The wafer
18
is held in place by applying a vacuum to the backside of the wafer (not shown). The wafer
18
can also be attached to the wafer carrier
26
by the application of a substrate attachment film (not shown) to the lower surface of the wafer carrier
26
. The wafer carrier
26
also rotates as indicated by arrow
32
, usually in the same direction as the polishing table
22
, at a rate on the order of 1 to 100 RPM. Due to the rotation of the polishing table
22
, the wafer
18
traverses a circular polishing path over the polishing pad
20
. A force
28
is also applied in the downward vertical direction against wafer
18
and presses the wafer
18
against the polishing pad
20
as it is being polished. The force
28
is typically in the order of 0 to 15 pounds per square inch and is applied by means of a shaft
30
that is attached to the back of wafer carrier
26
.
Accordingly, the subject surface (that is the lower surface) of the substrate
18
is polished by the combination of a chemical polishing action of alkali contained in the polishing agent or slurry
21
and a mechanical polishing action by silica contained in the polishing slurry
21
.
U.S. Pat. No. 5,775,983 (Shendon et al.) shows a conical roller for conditioning a pad.
U.S. Pat. No. 5,779,526 (Gill) show a polishing pad conditioning roller.
U.S. Pat. No. 5,681,212 (Hayakawa) shows a disk dresser.
U.S. Pat. No. 5,421,768 (Fijiwara et al.) shows a brush to clean a polishing pad.
U.S. Pat. No. 5,688,360 (Jairath) shows cylindrical and conical polishing pads.
SUMMARY OF THE INVENTION
It is therefore the primary objective of the present invention to provide a polishing device that can realize a high semiconductor wafer throughput and that exhibits uniformity and planarity or evenness of surface in the plane of the surface of the substrate that is to be polished.
The in-site roller dresser that is the subject of the present invention allows for the profile of the pad to be monitored while the roller is dressed or refurbished. This eliminates the need for destructive testing of the polishing pad. The in-site roller dresser at the same time eliminates the need for machine downtime for polishing pad profile determination since the polishing pad profile is dynamically tested and monitored during polishing operations. In conventional arrangements, the dresser is a disk, in the arrangement of the present invention the dresser is a roller type that can rotate around its axis in either direction. A sensor is provided with the diamond dresser that monitors the surface or profile of the polishing pad. Based on the data obtained by the sensor, the diamond dresser can be adjusted, which directly controls the polishing pad refurbishing action provided by the dresser.
In the first embodiment of the present invention the in-site roller dresser is manually controlled and adjusted for desired polishing pad profile and in accordance with a visually observed profile of the polishing pad as observed via an electronic display.
In the second embodiment of the present invention the in-site roller dresser is automatically controlled and adjusted for desired polishing pad profile. This adjustment is in accordance with a desired and predetermined polishing pad profile that is contained within the controlling mechanism of the polishing pad dresser.
REFERENCES:
patent: 5421768 (1995-06-01), Fujiwara et al.
patent: 5681212 (1997-10-01), Hayakawa et al.
patent: 5688360 (1997-11-01), Jairath
patent: 5775983 (1998-07-01), Shendon et al.
patent: 5779526 (1998-07-01), Gill
patent: 5885147 (1999-03-01), Kreager et al.
patent: 5944585 (1999-08-01), Nagahara et al.
patent: 5961373 (1999-10-01), Lai et al.
patent: 5997385 (1999-12-01), Ni
Chartered Semiconductor Manufacturing Ltd.
Morgan Eileen P.
Pike Rosemary L. S.
Saile George O.
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