Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2001-06-25
2004-10-19
Chowdhury, Tarifur R. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S054000
Reexamination Certificate
active
06806935
ABSTRACT:
BACKGROUND OF THE INVENTION
This application claims the benefit of Korean Patent Application No. P00-55034, filed on Sep. 19, 2000, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
This invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that is capable of eliminating a stain generated at an outer area of a thin film transistor array using an in-plane switching mode.
2. Discussion of the Related Art
Generally, a liquid crystal display of active matrix driving system uses thin film transistors (TFTs) as switching devices to display a natural moving picture. Since such a liquid crystal display can be made into a device that is smaller than a cathode ray tube (“CRT”), it is commercially available for use in monitors such as portable televisions, notebook personal computers and laptop personal computers, etc.
The active matrix liquid crystal display (LCD) displays a picture corresponding to video signals, such as television signals, on a pixel (or picture element) matrix having pixels arranged at each crossing of gate lines and data lines. Each pixel includes a liquid crystal cell for controlling transmitted light in accordance with a voltage level of a data signal from a data line. The TFT is installed at the crossing point of the gate line and the data line to switch a data signal to be transferred to the liquid crystal cell in response to a scanning signal (i.e., a gate pulse) from the gate line.
Such a liquid crystal display can be largely classified as twisted nematic (TN) mode, in which a vertical electric field is applied, and an in-plane switching (IPS) mode, in which a horizontal electric field is applied to have a wide viewing angle. How an LCD is classified depends on the direction of an electric field driving the liquid crystal.
The IPS mode LCD has an advantage over the TN mode LCD in that, in an IPS mode LCD, a liquid crystal within a pixel area is rotated in the horizontal direction by a horizontal electric field to have a wide viewing angle.
Referring to
FIG. 1
, the IPS mode LCD includes a TFT
50
provided at a crossing of a data line
52
and a gate line
54
, pixel electrodes
48
arranged in a matrix in a cell area between the data line
52
and the gate line
54
, and a common electrode
35
formed in parallel to the pixel electrodes
48
in the pixel area. As shown in
FIG. 2
, the TFT
50
is provided on a rear substrate
32
. The TFT
50
includes a gate electrode
34
connected to the gate line
54
, a source electrode
42
connected to the data line
52
, a drain electrode
44
connected to the pixel electrode
48
, and an active layer
38
defining a channel between the source electrode
42
and the drain electrode
44
.
The gate electrode
34
, the gate line
54
and the common electrode
35
are formed by depositing a metal such as chrome (Cr), etc. on the rear substrate
32
and then patterning it. Herein, the common electrode
35
is patterned into a plurality of strips within the pixel area. A gate insulating film
36
made from an inorganic dielectric material such as SiN
x
, etc. is entirely deposited on the rear substrate
32
provided with the gate electrode
34
, the gate line
54
and the common electrode
35
. Semiconductor layers consisting of the active layer
38
made from amorphous silicon (a-Si) and an ohmic contact layer
40
made from a-Si doped with n+ ions are disposed sequentially on the gate insulating film
36
. Then, the source electrode
42
, the drain electrode
44
and the data line
52
made from a metal material are provided to cover the semiconductor layers
38
and
40
. In this case, the source electrode
42
and the drain electrode
44
are patterned in such a manner to be spaced by a predetermined channel width from each other. Thereafter, indium-tin-oxide (ITO) is deposited and then patterned to form the pixel electrode
48
. Herein, the pixel electrode
48
is connected to the drain electrode
44
and is patterned into a plurality of strips that partially overlap and alternate with the common electrode
35
within the pixel area. Subsequently, an ohmic contact layer
40
is etched along a channel defined between the source electrode
42
and the drain electrode
44
to expose the active layer
38
. A protective film
46
made from SiN
x
or SiO
x
, etc. is entirely deposited on the rear substrate
32
to cover and thus protect the TFT
50
and the pixel electrode
48
.
As shown in
FIG. 3
, the rear substrate
32
, which is provided with the TFT array, is opposed to a front substrate
72
, which is provided with black matrices
74
and color filters
76
. A liquid crystal layer
78
is interposed between the rear and front substrates
32
and
72
. The pixel electrode
48
and the common electrode
35
oppose each other horizontally. When a gate high pulse is applied to the gate electrode
34
of the TFT
50
, an electric field corresponding to a difference voltage between a data voltage and a common voltage is applied between the pixel electrode
48
and the common electrode
35
. During a scanning period, a channel is defined between the source electrode
42
and the drain electrode
44
. Liquid crystal molecules in the liquid crystal layer
78
are driven with the horizontal electric field to control a quantity of transmitted light inputted from a back light.
Referring to
FIG. 4
, common lines
82
are formed on the rear substrate
32
in parallel to the gate lines
54
. The common lines
82
commonly apply a common voltage from an external driver to the common electrode
35
within a TFT array
90
. The common voltage lines
82
within the TFT array
90
are formed at an outer area adjacent to the TFT array
90
and are connected, via common voltage pads
80
, to the external driver. The gate line
54
is connected, via the gate pad
86
and a gate link
87
, to the external driver. The gate link
87
, formed at the outer area of the TFT array
90
, connects the gate line
54
to the gate pad
86
to deliver a gate voltage from the external driver to the TFT array
90
. Further, data pads, data links and data lines (not shown) for delivering a data voltage to the TFT array
90
are provided on the rear substrate
32
.
Referring again to
FIG. 3
, a liquid crystal
78
is injected between the rear substrate
32
and the front substrate
72
over the TFT array area, the gate pad area and the gate link area. In this case, the liquid crystal at the gate pad area and the gate link area is coupled with only a gate voltage applied to the gate link
87
, via the gate pad
86
upon driving of the LCD to thereby cause deterioration of the liquid crystal.
More specifically, an electric field corresponding to a voltage difference between a data voltage of the pixel electrode
48
and a common voltage of the common electrode
35
(wherein the pixel electrode
48
is horizontally opposed to the common electrode
35
for each cell) is applied to the liquid crystal
78
of the TFT array
90
when a gate high voltage is applied to the gate electrode
34
. Such electric field is maintained during a period when a gate low voltage is applied. By this horizontal electric field, the liquid crystal
78
is driven to control a quantity of a light transmitted from the back light. Generally, a data voltage having the opposite polarity for each successive frame is applied to the liquid crystal
78
to prevent deterioration of the liquid crystal. On the other hand, a gate voltage having the same polarity for each frame is applied to a liquid crystal at the outer area of the TFT array
90
, particularly, in the gate link area, for the majority of a frame period. More specifically, a gate high voltage of about +20V is applied to each gate line
54
for a relatively short time during one frame period. A gate low voltage of about −5V is supplied during the remaining portion of the frame period, which is the majority of the frame period. Thus, a gate low voltage having a direct current component is appli
Chowdhury Tarifur R.
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
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