In-plane switching mode liquid crystal display device...

Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only

Reexamination Certificate

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Details

C349S038000, C349S123000, C349S138000

Reexamination Certificate

active

06803982

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device, and more particularly to an in-plane switching mode liquid crystal display device, wherein the aperture ratio is improved, the driving voltage is decreased, and the fabricating cost is reduced.
Recently, the thin film transistor liquid crystal display device(TFT LCD) has been used as a display device of a portable television and a notebook computer, etc., but this TFT LCD has a small viewing angle.
In order to solve this problem, a twisted nematic LCD having optical compensation plates and a multi-domain LCD, etc., have been introduced. In these LCDs, however, since the contrast ratio depends on the viewing angle direction, the color of the image is shifted.
For a wide viewing angle, the in-plane switching mode LCD is disclosed in JAPAN DISPLAY 92 p547, Japanese Patent Unexamined Publication No. 7-36058, Japanese Patent Unexamined Publication No. 7-225538, and ASIA DISPLAY 95 P707, and etc.
FIG. 1
a
and
FIG. 1
b
are respectively plan and sectional views showing the conventional in-plane switching mode liquid crystal display device (IPS mode LCD), where
FIG. 1
b
is a sectional view taken along line A-A′ of
FIG. 1
a.
As shown in these figures, a gate bus line
1
and a data bus line
2
are formed on a first substrate
10
, defining a pixel. Although only one pixel is drawn in the figures, the real liquid crystal liquid display deice has a plurality of pixels. A common bus line
3
is aligned in the pixel, being parallel to the gate bus line
1
. A thin film transistor (TFT) is disposed at the cross of the gate and data bus lines
1
and
2
. As shown in
FIG. 1
b,
the TFT comprises a gate electrode
5
, agate insulator
12
, an active layer
15
, and n
+
layer
16
, a source electrode
6
, and a drain electrode
7
. In the pixel, a data electrode
8
and a common electrode
9
are formed parallel to the data bus line
2
. A portion of the data electrode
8
which overlaps the common bus line
3
is formed to obtain a storage capacitor which functions as maintaining a grey level voltage applied into the data electrode
8
. The common electrode
9
is connected to the common bus line
3
. The data electrode
8
is formed on the gate insulator
12
and is connected to the drain electrode
7
. The TFT, the data electrode
8
and the gate insulator
12
are covered with a passivation layer
20
. Thereon, a first alignment layer
23
a
is coated to determine the alignment direction.
On a second substrate
11
, a black mask
28
is formed to prevent a leakage of light through the regions of the TFT and the gate and data bus lines
1
and
2
. Thereon, a color filter layer
29
and a second alignment layer
23
b
are formed. Between the first and second substrates
10
and
11
, a liquid crystal layer
30
is formed.
When a voltage is applied to the conventional IPS mode LCD, electric field parallel to the substrates
10
and
11
is generated between the data and common electrodes
8
and
9
. Liquid crystal molecules in the pixel are rotated according to the electric field, controlling the amount of light passing through the liquid crystal layer
30
.
However, the conventional IPS mode LCD has the following problems.
Firstly, because the area for storage capacitor occupies quite a portion of the pixel region as well as the data and common electrodes are made of opaque metals, the aperture ratio is lowered.
Secondly, because the electric field applied to the LC layer is weakened by both the gate insulator
12
and the passivation layer
20
formed over the two electrodes
8
and
9
, the driving speed of the LC molecules is decreased, and consequently the driving voltage is increased.
Thirdly, because the data bus line
2
should be apart from the pixel region to the extent of not generating the crosstalk problem, the pixel region is decreased, thereby lowering the aperture ratio.
Fourthly, when the black mask is formed on the second substrate, the fabricating cost is increased and the aperture ratio is lowered by the inaccurate lamination of the two substrates.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an in-plane switching mode liquid crystal display device wherein the aperture ratio is improved, the driving voltage is decreased, and the fabricating cost is reduced.
In order to achieve the object, the in-plane switching mode liquid crystal display device comprises first and second substrates, a plurality of gate and data bus lines which are aligned on said first substrate to define a plurality of pixel regions, a common bus line aligned in said pixel regions of said first substrate, a thin film transistor formed at each of said pixel regions of said first substrate and comprising a gate electrode, a gate insulator, a semiconductor layer, a source electrode, and a drain electrode, a data electrode formed to be parallel to a first direction on said gate insulator and having a portion overlapping said common bus line for forming a first storage capacitor, a passivation layer formed over said data electrode and said thin film transistor, a common electrode formed on said passivation layer so as to overlap said gate and data bus lines and having a portion overlapping said data electrode for forming a second storage capacitor, and a liquid crystal layer formed between said first and second substrates.
Said common electrode is formed of ITO and is connected electrically to said common electrode through a first hole formed in said gate insulator and said passivation layer.
Said gate and data bus line may be formed of high conductive metal layers such as Mo metal layer, Mo/Al/Mo triple metal layers, or Cr/Al/Cr triple metal layers in order to prevent signal delay in said gate and data bus lines which is generated by being overlapped with said common electrode.
In the in-plane switching mode liquid crystal display device according to the present invention, the passivation layer and the gate insulator do not absorb the electric field applied to the liquid crystal layer because the common electrode is disposed above the two insulating layers. Accordingly, the driving voltage is lowered. Further, because the areas for storage capacitor can be decreased, the aperture ratio is much more improved. Furthermore, because the common electrode overlaps the gate and data bus lines to block the electric effect of the two bus lines, the crosstalk problem can be removed. Accordingly, the pixel region can be enlarged improving the aperture ratio. In addition, because the common electrode
109
is formed out of ITO to obtain IOP(ITO on passivation) structure, the contacting electric resistance between the pads and the driving circuits is decreased as well as the aperture ratio is improved.
According to another aspect of the present invention, the in-plane switching mode liquid crystal display device is provided, wherein said common electrode has an oblique side inclined relative to said first direction. The object of this embodiment is to prevent the problem in that disclination is generated in the region the common electrode crosses with the data electrode.
According to further aspect of the present invention, the in-plane switching mode liquid crystal display device is provided which further comprises a metal layer on said passivation layer in the region of said thin film transistor.
Said metal layer and said common electrode are formed of opaque metals including Mo, and function as black mask.
For obtaining IOP structure, said metal layer and said common electrode is formed of a double metal layer ITO/Mo which is formed by depositing Mo and indium tin oxide in the name order.
Said metal layer can be connected electrically to said data bus line through a second hole which is formed in said gate insulator and said passivation layer. In this case, the metal layer functions as a back gate electrode, increasing the switching speed of said thin film transistor.


REFERENCES:
patent: 5598285 (1997-01-01), Kondo et al.
patent: 5905556 (1999-05-01), Suzuki et al.
patent:

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