In-plane switching mode LCD with specific arrangement of...

Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal

Reexamination Certificate

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C349S141000

Reexamination Certificate

active

06335770

ABSTRACT:

BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to an in-plane switching mode liquid crystal display device.
B. Description of the Related Art
Recently, the thin film transistor liquid crystal display devices (TFT LCDS) have been used as display devices in such applications as portable televisions and notebook computers, but these TFT LCDs have small viewing angles.
In order to solve this problem, twisted nematic LCDs having, for example, optical compensation plates and multi-domains, have been introduced. In these LCDs, however, the color of the image is shifted because the contrast ratio depends on the viewing angle direction.
For a wide viewing angle, the in-plane switching mode LCD is disclosed, for example, in JAPAN DISPLAY 92 page 547, Japanese Patent Unexamined Publication No. 7-36058, Japanese Patent Unexamined Publication No. 7-225388, and ASIA DISPLAY 95 page 707.
FIG. 1
a
and
FIG. 1
b
are respectively plane and sectional views of the conventional in-plane switching mode liquid crystal display device (IPS mode LCD).
FIG. 1
b
is a sectional view taken along line A-A′ of
FIG. 1
a
. As shown in these figures, a gate bus line
1
and a data bus line
2
are formed on a first substrate
10
, defining a pixel. Although only one pixel is shown in the figures, a liquid crystal display device generally has a plurality of pixels. A common bus line
3
is aligned in the pixel, being parallel to gate bus line
1
. A thin film transistor (TFT) is disposed at the intersection of gate and data bus lines
1
and
2
. As shown in
FIG. 1
b
, the TFT comprises a gate electrode
5
, a gate insulator
12
, a semiconductor layer
15
, and an n
+
semiconductor layer
16
, a source electrode
6
, and a drain electrode
7
. In the pixel, a data electrode
8
and a common electrode
9
are formed parallel to data bus line
2
. A portion of data electrode
8
which overlaps common bus line
3
is formed to obtain a storage capacitor, which functions as maintaining a grey level voltage applied into data electrode
8
. Common electrode
9
is connected to common bus line
3
. Data electrode
8
is formed on gate insulator
12
and is connected to drain electrode
7
. The TFT, data electrode
8
and gate insulator
12
are covered with a passivation layer
20
. Thereon, a first alignment layer
23
a
is coated to determine the alignment direction.
On a second substrate
11
, a black mask
28
is formed to prevent a leakage of light through the regions of the TFT and gate and data bus lines
1
and
2
. Thereon, a color filter layer
29
and a second alignment layer
23
b
are formed. Between first and second substrates
10
and
11
, a liquid crystal layer
30
is formed.
When a voltage is applied to the conventional IPS mode LCD, electric field parallel to substrates
10
and
11
is generated between data and common electrodes
8
and
9
. Liquid crystal molecules in the pixel are rotated according to the electric field, controlling the amount of light passing through liquid crystal layer
30
.
However, the conventional IPS mode LCD has the following problems.
First, because the area for storage capacitor occupies quite a portion of the pixel region and because the data and common electrodes are made of opaque metals, the aperture ratio is lowered.
Second, because the electric field applied to the LC layer is weakened by both gate insulator
12
and passivation layer
20
formed over two electrodes
8
and
9
, the driving speed of the LC molecules is decreased, and consequently the driving voltage is increased.
Third, because data bus line
2
should be apart from the pixel region so as to avoid the crosstalk problem, the pixel region is decreased, thereby lowering the aperture ratio.
Fourth, when the black mask is formed on the second substrate, the fabricating cost is increased and the aperture ratio is lowered to compensate for the imprecise lamination of the two substrates.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an in-plane switching mode liquid crystal display device wherein the aperture ratio is improved.
Another object of the present invention is to provide an in-plane switching mode liquid crystal display device wherein the driving voltage is decreased.
A further object of the present invention is to reduce the fabricating cost of provide an in-plane switching mode liquid crystal display device.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the in-plane switching mode liquid crystal display device of the present invention comprises: a substrate; a plurality of gate and data bus lines over the substrate, defining a plurality of pixel regions; a common bus line aligned in the pixel regions; a gate insulator over the common bus line; a data electrode over the gate insulator and having a portion overlying the common bus line to form a first storage capacitor; a passivation layer over the data electrode; and a common electrode over the passivation layer at least partially overlying the gate and data bus lines and at least partially overlying the data electrode to form a second storage capacitor.
According to another aspect of the present invention, the in-plane switching mode liquid crystal display device comprises: a substrate; a plurality of gate and data bus lines over the substrate, defining a plurality of pixel regions; a common bus line aligned in the pixel regions; a gate insulator over the common bus line; a thin film transistor coupled to each of the pixel regions and including at least a part of the gate insulator; a data electrode over the gate insulator and having a portion overlying the common bus line to form a first storage capacitor; a passivation layer over the data electrode and the thin film transistor; a common electrode over the passivation layer and at least partially overlying the data electrode to form a second storage capacitor; and a metal layer over the passivation layer and the thin film transistor.
According to a further aspect of the present invention, the in-plane switching mode liquid crystal display device comprises: first and second substrates having a plurality of pixel regions; a common bus line aligned in the pixel regions; a first insulating layer over the common bus line; a data electrode over the first insulating layer and having a portion overlying the common bus line to form a first storage capacitor; a second insulating layer over the data electrode; a common electrode over the second insulating layer, the common electrode having one or more openings, at least one of the openings having a substantially rectangular shape with four corner areas, at least one corner area being cut at an angle, and the common electrode having a portion overlying the data electrode to form a second storage capacitor; and a liquid crystal layer formed between the first and second substrates.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5321535 (1994-06-01), Ukai et al.
patent: 5459596 (1995-10-01), Ueda et al.
patent: 5576858 (1996-11-01), Ukai et al.
patent: 5646705 (1997-07-01), Higuchi et al.
patent: 5760856 (1998-06-01), Yanagawa et al.
patent: 5760857 (1998-06-01), Yanagawa et al.
patent: 5781261 (1998-07-01), Ohta et al.
patent: 5786876 (1998-07-01), Ota et al.
patent: 5818560 (1998-10-01), Kouno et al.
patent: 5852485 (1998-12-01), Shimada et al.
patent: 5886762 (1999-03-01), Lee et al.
patent: 5946060 (1999-08-

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