In phase alignment for PLL's

Details In phase alignment for PLL's In phase alignment for PLL's

2000-01-28

2001-07-24

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S150000, C327S162000, C331SDIG002, C375S376000

Reexamination Certificate

active

06265919

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of electronic circuits and, more particularly, to phase locked loop circuits with improved noise immunity and phase alignment.
DESCRIPTION OF THE RELATED ART
In general, a phase locked loop or PLL is an electronic circuit that controls a variable oscillator so that the oscillator maintains a constant phase angle relative to a reference signal. In operation, a PLL circuit will ‘lock on’ to an input and track its frequency and phase relationship. A PLL circuit can be used to synthesize or generate a frequency and maintain the phase of the generated signal to the reference. It can also be used to synchronize signals (or clocks) to a reference. PLL circuits are often incorporated in the clock systems of radio, television, satellite and telecommunication (e.g., mobile and cellular) systems. Basic PLL circuits typically include a lowpass filter (LPF), a voltage controlled oscillator (VCO), a phase detector and an integrating amplifier.
In typical cellular telephone or mobile communication applications, the output signal frequency (and the associated system clock) of the mobile device must be switched between a plurality of frequencies. However, switching the system clock can cause glitching in the associated PLL circuits and may disrupt the logic circuits that the system clock is driving. An effective way of reducing glitching in PLL circuits is to improve the phase detector by using exclusive-or (XOR) logic.
A typical XOR PLL is shown in FIG.
1
. R
1
a,
R
1
b,
and C
1
form a low-pass filter. RF is used to set the gain of the op-amp. Cfa forms an integrator and Cfb is used to improve high frequency stability. R
2
a,
R
2
b
and C
2
are used to bias the op-amp at VCC/2. The optional divider can be used to synthesize frequencies other than the reference input frequency. The output of the VCO is coupled to the XOR phase detector which greatly improves glitch immunity when switching the reference clock.
However, XOR PLL circuits lock onto the quadrature of the reference clock. This is often undesirable in a digital circuit. In order to eliminate this quadrature phase offset, dividers can be coupled to both inputs of the XOR phase detector as shown in FIG.
2
. The VCO output is divided by 4 to produce a {fraction (1/4 )} frequency signal. Since the frequency being locked onto is {fraction (1/4 )} of the reference and local frequencies, the phases of the reference and the local frequencies are automatically aligned. However, PLL circuits of this type suffer from glitch memory.
Another solution to the quadrature problem is the use of an edge sensitive phase detector. In the alternative, a digital phase detector using flip flops may be used. These types of PLL circuit are sensitive to glitching and the PLL circuit may be perturbed for many cycles after a glitch.
It would be desirable to provide a simple PLL circuit design with a low sensitivity to glitching while also providing a phase aligned output.
SUMMARY OF THE INVENTION
The present invention is directed to an improved PLL which produces an output signal that is in-phase with the reference clock input despite switching of the reference clock. A quadrature signal is generated using a quadrature decoder having a counter, a state decoder and a flip flop. A local oscillator having a local clock frequency which is a multiple of the reference clock frequency is provided. The local clock output is divided down with a binary counter to match the reference clock frequency. The counter state is decoded using an AND gate in combination with a flip flop. The divided clock output is then re-synchronized with the reference clock using the local clock coupled to the clock input of the flip flop. The output of the flip flop is a quadrature copy of the reference clock, and this quadrature signal is fed back to the phase detector. The resulting circuit overcomes the quadrature offset problem of typical XOR PLL circuits while retaining the noise and glitch immunity of such circuit arrangements.


REFERENCES:
patent: 4456884 (1984-06-01), Yarborough, Jr.
patent: 4972442 (1990-11-01), Steierman
patent: 5415046 (1995-05-01), Guinon

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