In-memory preprocessor for compounding a sequence of instruction

Boots – shoes – and leggings

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364230, 3642303, 3642319, 3642624, 364263, 364DIG1, G06F 940

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053554604

ABSTRACT:
A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.

REFERENCES:
patent: 3401376 (1968-09-01), Barnes et al.
patent: 4025771 (1977-05-01), Lynch, Jr. et al.
patent: 4295193 (1981-10-01), Pomerene
patent: 4439828 (1984-03-01), Martin
patent: 4594655 (1986-06-01), Hao et al.
patent: 4847755 (1989-07-01), Morrison et al.
patent: 5021945 (1991-06-01), Morrison et al.
Acosta, R. D., et al., "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors", IEEE Transactions on Computers, Fall, C-35 No. 9, Sep. 1986, pp. 815-828.
Anderson, V. W., et al., the IBM System/360 Model 91: "Machine Philosophy and Instruction Handling", computer structures: Principles and Examples (Siewiorek, et al.,) ed (McGraw-Hill, 1982,) pp. 276-292.
Capozzi, A. J., et al., "Non-Sequential High-Performance Processing" IBM Technical Disclosure Bulletin, vol. 27, No. 5, Oct. 1984, pp. 2842-2844.
Chan, S., et al., "Building Parallelism into the Instruction Pipeline", High Performance Systems, Dec., 1989, pp. 53-60.
Murakami, K., et al., "SIMP (Single Instruction Stream/Multiple Instruction Pipelining): A Novel High-Speed Single Processor Architecture", Proceedings of the Sixteenth Annual Symposium on Computer Architecture, 1989, pp. 78-85.
Smith, J. E., "Dynamic Instructions Scheduling and the Astronautics ZS-1", IEEE Computer, Jul., 1989, pp. 21-35.
Smith, M. D., et al., "Limits on Multiple Instruction Issue", ASPLOS III, 1989, pp. 290-302.
Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", Computer Structures, Principles, and Examples (Siewiorek, et al. ed), McGraw-Hill, 1982, pp. 293-302.
Wulf, P. S., "The WM Computer Architecture", Computer Architecture News, vol. 16, No. 1, Mar. 1988, pp. 70-84.
Jouppi, N. P., et al., "Available Instruction-Level Parallelism for Superscalar Pipelined Machines", ASPLOS III, 1989, pp. 272-282.
Jouppi, N. P., "The Non-Uniform Distribution of Instruction-Level and Machine Parallelism and its Effect on Performance", IEEE Transactions on Computers, vol. 38, No. 12, Dec., 1989, pp. 1645-1658.
Ryan, D. E., "Entails 80960: An Architecture Optimized for Embedded Control", IEEE Microcomputers, vol. 8, No. 3, Jun., 1988, pp. 63-76.
Colwell, R. P., et al., "A VLIW Architecture for a Trace Scheduling Complier", IEEE Transactions on Computers, vol. 37, No. 8, Aug., 1988, pp. 967-979.
Fisher, J. A., "The VLIW Machine: A Multi-Processor for Compiling Scientific Code", IEEE Computer, Jul., 1984, pp. 45-53.
Berenbaum, A. D., "Introduction to the Crisp Instruction Set Architecture", Proceedings of Compcon, Spring, 1987, pp. 86-89.
Bandoyopadhyay, S., et al., "Compiling for the CRISP Microprocessor", Proceedings of Compcon, Spring, 1987, pp. 96-100.
Hennessy, J., et al., "MIPS: A VSI Processor Architecture", Proceedings of the CMU Conference on VLSI Systems and Computations, 1981, pp. 337-346.
Patterson, E. A., "Reduced Instruction Set Computers", Communications of the ACM, vol. 28, No. 1, Jan., 1985, pp. 8-21.
Radin, G., "The 801 Mini-Computer", IBM Journal of Research and Development, vol. 27, No. 3, May, 1983, pp. 237-246.
Ditzel, D. R., et al., "Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero", Proceedings of Compcon, Spring 1987, pp. 2-9.
Hwu, W. W., et al., "Checkpoint Repair for High-Performance Out-of -Order Execution Machines", IEEE Transactions on Computers vol. C36, No. 12, Dec., 1987, pp. 1496-1594.
Lee, J. K. F., et al., "Branch Prediction Strategies in Branch Target Buffer Design", IEEE Computer, vol. 17, No. 1, Jan. 1984, pp. 6-22.
Riesman, E. M., "The Inhibition of Potential Parallelism by Conditional Jumps", IEEE Transactions on Computers, Dec., 1972, pp. 1405-1411.
Smith, J. E., "A Study of Branch Prediction Strategies", IEEE Proceedings of the Eight Annual Symposium on Computer Architecuture, May 1981, pp. 135-148.
Archibold, James, et al., Cache Coherence Protocols: "Evaluation Using a Multiprocessor Simulation Model", ACM Transactions on Computer Systems, vol. 4, No. 4, Nov. 1986, pp. 273-398.
Baer, J. L., et al., "Multi-Level Cache Hierarchies: Organizations, Protocols, and Performance" Journal of Parallel and Distributed Computing vol. 6, 1989, pp. 451-476.
Smith, A. J., "Cache Memories", Computing Surveys, vol. 14, No. 3 Sep., 1982, pp. 473-530.
Smith, J. E. et al., "A Study of Instruction Cache Organizations and Replacement Policies", IEEE Proceedings of the Tenth Annual International Symposium on Computer Architecture, Jun. 1983, pp. 132-137.
Vassiliadis, S., et al., "Condition Code Predictory for Fixed-Arithmetic Units", International Journal of Electronics, vol. 66, No. 6, 1989, pp. 887-890.
Tucker, S. G., "The IBM 3090 System: An Overview", IBM Systems Journal, vol. 25, No. 1, 1986, pp. 4-19.
IBM Publication No. SA22-7200-0, Principles of Operation, IBM Enterprise Systems Architecture/370, 1988.
The Architecture of Pipelined Computers, by Peter M. Kogge Hemisphere Publishing Corporation, 1981.
IBM Technical Disclosure Bulletin (vol. 33 No. 10A, Mar. 1991), by R. J. Eberhard.

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