In-line scan control apparatus for data processor testing

Details In-line scan control apparatus for data processor testing In-line scan control apparatus for data processor testing

1986-03-31

1988-01-05

Smith, Jerry

Excavating

371 27, G01R 3128

Patent

active

047180650

ABSTRACT:
Apparatus is disclosed for generating pseudo-random bit patterns that are applied to a data processor, or other digital logic unit, for test purposes. In accordance with the invention, certain of the elemental storage units (e.g., flipflops) of the data processor are designed for two-mode operation: A normal mode of operation during which they operate as a part of the data processor in normal fashion, and a scan mode operation during which the elemental storage units respond to scan control signals to form a number of shift register or scan line configurations for receiving the pseudo-random sequenced or non-random sequenced test patterns generated by the apparatus. During testing, the bit patterns are passed through the scan line configurations and applied to compression circuits where, using cyclic redundancy checking (CRC), compression bit patterns received from the scan lines are achieved. Produced are test signatures that are stored in a memory for later comparison with standardized signatures to determine the PASS/FAIL condition of the processor. Tests can be preceded and followed by a controlled scan of the digital logic to save and restore the operational state of the digital logic. In this manner, test interruptions are relatively unobtrusive and essentially transparent to the logic tested.

REFERENCES:
patent: 4326290 (1982-04-01), Davis
patent: 4513418 (1985-04-01), Bardell
patent: 4534028 (1985-08-01), Trischler
patent: 4575674 (1986-03-01), Bass
patent: 4602210 (1986-07-01), Fasang

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