In-line non-contact depletion capacitance measurement method...

Details In-line non-contact depletion capacitance measurement method... In-line non-contact depletion capacitance measurement method...

1999-08-26

2001-07-24

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754120

Reexamination Certificate

active

06265890

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT REGARDING FEDERALLY
SPONSORED RESEARCH OR DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor wafer testing, and more particularly to a non-contact semiconductor method and apparatus for depletion capacitance measurement of a semiconductor wafer.
2. Description of Related Art
In recent years, gate dielectric thickness of semiconductor wafers has been greatly reduced, and is now approaching both the pinhole and tunneling limits for conventional silicon oxides. During the past ten years, gate oxide dielectric thickness has decreased at an average rate of twelve percent per year. Simultaneously, gate oxide operating fields have increased at approximately 10 percent per year. As we enter the gigabit era, sub-0.25 micron design rules are pushing oxide thickness below 60 Å. New dielectrics, such as lightly nitrided oxides, stacked oxides, and high-k materials, are being developed to meet performance and reliability requirements.
Aggressive oxide scaling and field enhancement have substantially improved low power device performance, but they have also increased the importance of accurate physical and electrical gate oxide characterization. Physical characterization of thin oxides and interfaces has evolved substantially during the past three decades, partly because of developments in ellipsometry, high resolution TEM, x-ray, electron diffraction, and micro-Raman spectroscopy. In contrast, few improvements have been made to electrical characterization methods. Consequently, commercially available non-contact electrical characterization has not kept pace with dielectric thickness developments.
Contact electrical characterization techniques for measuring properties of a semiconductor wafer are available, but they are both inefficient and costly to use. By way of example, capacitance-voltage (C-V), current-voltage (I-V), and full-flow device characterization are effective, but these techniques can only be performed on functioning wafers, meaning that significant semiconductor wafer processing generally must occur before they can be used. Additionally, wafers which have been contaminated during measurement usually are not reused. In contrast, non-contact characterization can be achieved without significantly completing the wafer fabrication process, which speeds process development in research and development facilities. Non-contact measurement also offers significant cost benefits because non-contact techniques seldom damage electrical test wafers.
The significant distinction between contact and non-contact techniques is further illustrated by
FIGS. 1 and 2
, in which steps of a conventional contact electrical process monitoring technique, metal oxide semiconductor capacitor (MOSCAP) C-V, can be compared to the steps required for a typical in-line, non-contact technique.
FIG. 1
specifically depicts an example of a process flow for MOSCAPs
10
, which begins with oxidation of a substrate
12
. In
FIG. 1
, the oxidized substrate is exposed to sputtering according to the step of block
14
, during which the oxide film on the substrate's surface can be damaged. The substrate is further exposed to the application of photoresist according to the step of block
16
, and photolithography and other development according to the step of block
18
. The surface next undergoes dry etching and cleaning, in accordance with block
20
, which can damage the wafer's surface. After dry etching and cleaning, gas annealing occurs in order to repair damage which has occurred to the wafer during this process
10
, according to the step of block
22
. After annealing, C-V measurements can be taken for the wafer's surface, according to the step of block
24
, and the results can be provided to a process observer, according to the step of block
26
. Thus, sputtering, dry etching and cleaning, and/or gas annealing may modify the initial oxide properties of the wafer. Poly-MOSCAP processing, often used on thin gate oxides to prevent metal punch-through, can modify the initial oxide quality still further. Additionally, significant wafer fabrication occurs before measurements are obtained.
In contrast, in-line, non-contact measurement is more efficient, and avoids damage to the surface being monitored.
FIG. 2
illustrates an in-line, non-contact measurement process
30
, in which a wafer's surface is oxidized
32
, in-line, non-contact measurements are taken
34
, and the results of the measurements are rapidly provided to a process observer
36
. The elimination of several process steps which can damage the quality of the oxide layer on the wafer's surface saves time and protects the oxide layer.
Currently, there are several commercially available options for in-line, contact monitoring of oxide and silicon quality, but each of these contact methods has significant disadvantages. One such method is the film gap technique, which can characterize oxide charge, near surface doping, near surface recombination lifetime, and density of interface traps. The underlying principal of the film gap technique is similar to that of a high-frequency C-V plotter, in which a DC electrical bias is swept while an AC stimulus is applied to the silicon. During the film gap method, the stimulus is a modulated light source, and the AC photoresponse is capacitively coupled to a transparent electrode which is separated from the sample by a Mylar™ film. Although this technique is compact and relatively inexpensive, the Mylar™ sheet cannot withstand high temperatures, preventing mobile charge testing. The contacting nature of the technique sometimes results in cross-contamination between wafers, and therefore damage to the oxide layer. Additionally, any probes which are used for measuring must be carefully monitored for charge build-up in order to avoid false detection of oxide charge.
Mercury probe analysis is another well-established, in-line, non-contact technique which is suitable for monitoring a wide variety of oxides. In particular, the technique can measure the electrical properties of very leaky oxides because the mercury probe can source a large compliance current. During this process, a mercury “dot” is placed on the wafer. Conventional reliability testing metrics such as charge (Q) and current density-voltage (J-V) analysis can be carried out with mercury probe stations. Although C-V monitoring is also possible with mercury probes, the technique does not lend itself to mobile charge analysis since the mercury dot cannot be heated. Wafers are usually not reused after exposure to mercury, and high speed scanning techniques that rely on photovoltaic effect cannot be used due to the opaque nature of the mercury electrode.
Bulk diffusion length measurement provides a third in-line, contact method. With this technique, several different wavelengths of light generate photoinduced carriers, and the surface photovoltage signal is monitored as a function of the light penetration depth. Samples with a long diffusion length will allow carriers generated deep in the silicon bulk to diffuse back to the surface, while samples with low bulk diffusion length or lifetime will have little photoresponse to long-wavelength photoexcitation. This technique excels in monitoring bulk silicon quality when the bulk diffusion length is less than half the wafer thickness, and may be combined with temperature cycling to generate maps of bulk iron concentration.
Recently, mathematical modeling of the assumed front and rear wafer surface recombination rates has become necessary to extract the bulk diffusion length from today's higher quality silicon. Thus, the condition of the wafer's surface at the front and the back of the sample plays an increasing role in the measurement response as bulk lifetime increases, and variations in surface recombination velocity, which is strongly bias dependent, cause difficulties when using this technique. Significantly, this technique w

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