In-circuit emulator in which abrupt and deferred arming and disa

Details In-circuit emulator in which abrupt and deferred arming and disa In-circuit emulator in which abrupt and deferred arming and disa

1995-04-17

1998-05-26

Harrell, Robert B.

G06F 1130

Patent

active

057580596

ABSTRACT:
An in-circuit emulator on an integrated circuit chip having an input pin for externally triggering on-chip break mechanisms. A first break logic having a first arm input is connected to an instruction pointer counter (IP counter). The first break logic matches the IP counter to a first instruction execution address. A second break logic having a second arm input is connected to the IP counter. The second break logic matches the IP counter to a second instruction execution address and a third instruction execution address occurring a fixed time interval after the second instruction execution address in a mutistage pipe line of instructions. A sequencer logic connected to the input pin, the first arm input and the second arm input activates the second arm input after the input pin has been active for 1 cycle. The sequencer logic activates the first arm input after the input pin has been active for 2 cycles. Also provided is a fast and permanent break logic having an abrupt permanent beak input connected to the sequencer and a fast break input connected to the sequencer. The sequencer activates the abrupt permanent beak input after the input pin has been active for 3 cycles. The sequencer activates the fast break input after the input pin has been active for 4 cycles. This allows external abrupt and deferred arming and disarming of internal fast and permanent events, using the same input pin as was used in the past for just an abrupt break.

REFERENCES:
patent: 4674089 (1987-06-01), Poret et al.
patent: 4998197 (1991-03-01), Kurakazu et al.

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