In-between phase clamping circuit to reduce the effects of posit

Details In-between phase clamping circuit to reduce the effects of posit In-between phase clamping circuit to reduce the effects of posit

1976-08-25

1977-08-16

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307221C, 307237, H03K 1716, H03K 1908, H03K 1760, H03K 508

Patent

active

040428338

ABSTRACT:
An improved MOS clamping circuit compatible with a multi-phase, major-minor clocking scheme. The present circuit is adapted to clamp the output terminal of a conventional major logic gate to a negative signal level. The instant clamping circuit prevents the deterioration of the logic gate output signal as a consequence of positive noise during the minor clock phases and during an in-between clock phase, which phase corresponds to the interval of time between the occurrence of first and second major clock phases.

REFERENCES:
patent: 3567968 (1971-03-01), Booher
patent: 3579275 (1971-05-01), Polkinghorn et al.
patent: 3631261 (1971-12-01), Heimbigner
patent: 3646369 (1972-02-01), Fujimoto
patent: 3708688 (1973-01-01), Yao
patent: 3774053 (1973-11-01), Carlson

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