Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2000-12-04
2002-06-18
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S297000, C327S261000
Reexamination Certificate
active
06407607
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention refers to signal generation for the purpose of measuring delay of a signal through a network and more particular measuring wire coupling capacitance that delays a signal in an integrated circuit.
2. Description of Related Art
In deep sub-micron integrated circuits wire capacitance is dominated by coupling capacitance to adjacent wires. The adjacent wires can be either wires in the same plane that lay side beside or on different wiring planes where the coupling capacitance occurs where areas of wires lay on top of one another separated by an insulator. The coupling of signals through the coupling capacitance can cause substantial delay to a signal depending on whether the direction of switching is in the same direction or different direction.
In U.S. Pat. No. 6,005,829 (Conn) describes a method is directed to characterizing interconnect timing using a reference ring oscillator circuit. In U.S. Pat. No. 5,923,676 (Sunter et al.) describes a BIST architecture directed to the measurement of integrated circuit delays in combinatorial and sequential logic. In U.S. Pat. No. 5,761,081 (Tomita et al.) describes a method directed to evaluating signal propagation delay in an integrated inverter circuit chain. In U.S. Pat. No. 4,876,501 (Ardini et al.) describes a method and apparatus directed to accurately measure of VLSI devices with a test instrument having errors comparable to the delays being measured. In U.S. Pat. No. 4,392,105 (McLeod) describes a test circuit directed to delay measurements on an LSI chip containing two oscillating loops with one loop containing the circuit under test.
Testing for the coupling effects between wires in integrated circuits is made difficult by the length that wires run in parallel and whether the signals on the wires that are coupled by capacitance are switching in the same direction or opposite directions. Ideally, if two wires coupled by capacitance have two signals that switch at exactly the same time in the same direction and with the same amplitude, there will be no energy transfer through the coupling capacitance and there will be no observable effect on the delay of one signal upon the other. In this case the effective coupling capacitance is thought to be zero. If the same two wires have two signals which switch in opposite directions at exactly the same time, there will be a maximum transfer of energy between the two wires resulting in the increased the delay of the signals. If the amplitude of the two signals of opposite direction are equal, then the effective coupling capacitance is twice the physical capacitance. As the timing of the two signals vary from being in phase to being out of phase and the amplitude of the two signals vary, the effective coupling capacitance varies from zero to twice the physical coupling capacitance.
In
FIG. 1
is shown a wire
10
coupled to two additional wires,
11
and
12
, on the same wiring plane and coupled to a third wire
13
on an adjacent wiring plane. The capacitance, Cc, is the coupling capacitance between the parallel lengths of wire running on the same wiring plane. The capacitance, Cc, is determined by the geometry of the routed wires and the dielectric located in between. The coupling capacitance, Ca, between wires on different planes is a result of the area of the two wires that are in parallel, such as the area where one wire crosses over a second wire. If one wire,
13
, is larger than a second wire,
10
, a fringing capacitance, Cf, may add substantially to the coupling capacitance, Ca.
In
FIG. 2
a
a plan view is shown of the routing of three wires on a wiring plane. A signal wire
20
is routed between and in parallel with two other wires
21
and
22
. A signal S
1
enters signal wire
20
at the parallel routing of the three wires and exits from the parallel combination at So
1
. Wires
21
and
22
have signals
11
and
12
that couple energy to the signal wire
20
through capacitance C
1
and C
2
and distort and slow the signal S
1
. In
FIG. 2
b
is shown the plane view of two wires
25
and
26
that are routed in parallel on separate planes. Wire
26
being routed on a lower wiring plane is symbolized by the dashed lines and the area of overlap that produces the coupled capacitance is symbolized squares where the two wires are routed over one another. The capacitance C
3
, shown in
FIG. 2
c
, is the capacitance of each individual area where the two wires cross each other. A summation of all the incremental capacitance represented by C
3
forms the coupling capacitance between signal wire
25
and coupling wire
26
. A signal S
2
entering one end of wire
25
will be adversely affected by the coupling affect caused by C
3
and the signal will reach the output So
2
after being delayed in addition to the wire delay by the coupling capacitance.
As integrated circuits get smaller the affect of coupling on the delay of a circuit will increase. Because of all the variables it is difficult to predict how much the increased delay due to coupling is. A capability is needed to form various coupling arrangements and measure the affects of combinations of signals applied to wires that are in parallel.
SUMMARY OF THE INVENTION
An objective of the present invention is to generate a signal that has been delayed by energy coupled from adjacent parallel wires. It is further and objective of the present invention to produce delayed signals with in phase and out of phase coupling affects for both positive and negative signal transitions. It is also an objective of the present invention to produce an in phase and out of phase signal generator that is capable of being coupled to additional stages to produce a delay between an input and an output of the last stage that can be easily measured. It is further an objective of the present invention to be able to couple additional stages without the signal becoming out of phase with the test setup signals.
A first stage of a signal generating circuit for delaying in phase and out of phase signals is demonstrated. An N-stage signal generating circuit is described that is constructed from concatenating N-stages of the first stage together where the output from a stage drives the enable input of the next stage. Different modes are shown which include in phase, out of phase and quiescent coupling. The signal generating circuits are a cell-based design that can be easily implemented in CMOS technology.
REFERENCES:
patent: 4392105 (1983-07-01), McLeod
patent: 4876501 (1989-10-01), Ardini et al.
patent: 5761081 (1998-06-01), Tomita et al.
patent: 5923676 (1999-07-01), Sunter et al.
patent: 6005829 (1999-12-01), Conn
patent: 6263483 (2001-07-01), Dupenloup
patent: 0124429 (1998-12-01), None
Ackerman Stephen B.
Le Dinh T.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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