Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-11-16
2002-01-08
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C257S510000
Reexamination Certificate
active
06337256
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a layer for precluding segregation of impurity ions which prevents impurity ion permeation between a device isolation region and a semiconductor substrate, a fabrication method thereof, an isolation structure for a semiconductor device using the segregation precluding layer and a fabrication method thereof.
2. Description of the Conventional Art
A LOCOS (local oxidation of silicon) structure using a LOCOS method has been often used as an isolation structure of a conventional semiconductor device, but there is limit to improvement of integration of the semiconductor device due to generation of a bird's beaks thereof. Thus, there is a tendency to adopt an STI (shallow trench isolation) or PGI (profiled groove isolation) structure in which a trench or a groove is formed in a semiconductor substrate as a device isolation structure and then an insulator is filled therein.
FIG. 1
is a plan diagram illustrating a cell array unit of a semiconductor device, particularly, a DRAM (dynamic random access memory). A semiconductor substrate
100
is divided into an active region
101
and a non-active region
102
which covers the active region
101
, the non-active region
102
being called a device isolation region. The active region is a part where a semiconductor device, that is, a transistor is formed and in which impurity ions are implanted, thus a source
101
a
and a drain
101
b
are provided. The device isolation region
102
electrically isolates the semiconductor device and has the STI or PGI structure. A gate electrode
104
is formed on the active region
101
. A channel of the transistor is formed in a portion of the semiconductor substrate where the active region
101
and the gate electrode
104
are overlapped.
FIG. 2A
is a cross-sectional vertical view taken along the line IIa—IIa of
FIG. 1
, the line horizontally crossing the active region
101
in a center point of a channel width of the transistor. As shown therein, the active region
101
of the semiconductor substrate
100
is covered by the device isolation region
102
. The device isolation region
102
is etched to a predetermined depth (for example, about 0.5-0.8 mm), thereby forming a trench
102
a
and an insulator
102
b
is filled therein. The source
101
a
and the drain
101
b
, as shown in
FIG. 1
, are provided in the semiconductor substrate
100
having a predetermined distance and a gate insulating film
103
and a gate electrode
104
are formed on the semiconductor substrate
100
.
While,
FIG. 2B
is a cross-sectional vertical view taken along the line IIb—IIb of
FIG. 1
, the line being perpendicular to the line IIa—IIa of FIG.
1
. As shown therein, the trench or groove
102
a
is formed in the semiconductor substrate
100
and the insulator
102
b
is filled in the trench or groove
102
a
. Here, the part
102
in which the insulator is filled corresponds to the device isolation region. The gate insulating film
103
is formed on the semiconductor substrate
100
and a gate electrode
104
is formed thereon, the gate electrode
104
being formed in the active region
101
and extended to the upper surface of the device isolation region
102
.
101
c
is a part where impurity ions in the semiconductor substrate segregate to the device isolation region and thus density thereof is considerably low. Also,
101
d
is a center part of the channel region of the transistor.
However, the conventional semiconductor device having the STI or PGI structure, particularly the semiconductor which is an N-channel transistor has problems as follows.
The N-channel transistor is generally formed in a p-type semiconductor substrate or in a p-type well. Impurity ions, in particular, boron ions in the p-type semiconductor substrate or the p-type wall have a tendency to easily segregate to the device isolation region and accordingly the density of the impurity ions of a portion adjacent to the device isolation region, that is, a portion
101
c
of the semiconductor substrate adjacent to a sidewall of the trench
102
a
becomes decreased. Accordingly, an impurity depletion layer is formed in the semiconductor substrate along the sidewall of the trench. As a result, in the center part
101
d
of the channel region the channel of the transistor is normally formed above a threshold voltage in accordance with a voltage applied to the gate electrode, but in the channel region adjacent to the device isolation region a channel is easily formed below the threshold voltage, so that the threshold voltage decreases. In addition, an electrical characteristic of the semiconductor device is unstable that, for example, a subthreshold current increases and a subthreshold current curve has a hump, which results in the deterioration of the semiconductor device.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an impurity ion segregation precluding layer, a fabrication method thereof, an isolation structure for semiconductor device using the impurity ion segregation precluding layer and a fabricating method thereof which obviate the problems and disadvantages in the conventional art.
An object of the present invention is to provide an impurity ion segregation precluding layer and a fabrication method thereof that prevent impurity ions in a semiconductor substrate from permeating into a device isolation region thereof.
Also, an object of the present invention is to provide an isolation structure of a semiconductor device and a fabrication method thereof that stabilize electric characteristics of a semiconductor device using the above impurity ion segregation precluding layer and thereby improve reliability thereof.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided an impurity ion segregation precluding layer having a thickness of 1-10 A by placing a semiconductor substrate formed of silicon in a high-temperature furnace and annealing the semiconductor substrate while flowing a nitride gas thereinto at at least 20 l/min.
Also, to achieve the above objects of the present invention, there is provided an isolation structure of a semiconductor device, which includes a semiconductor substrate, a trench formed in a predetermined portion of the semiconductor substrate, an impurity ion segregation precluding layer formed on a surface of the trench, and an insulator filled in the trench, the impurity ion segregation precluding layer being obtained by placing the semiconductor substrate into a furnace at a high temperature and annealing the semiconductor substrate flowing a nitride gas into the furnace at about 20 l/min.
Also, to achieve the above objects of the present invention, there is provided a method for fabricating an isolation structure of a semiconductor device, which includes forming a trench in a portion of a semiconductor substrate formed of silicon corresponding to a device isolation region, placing the semiconductor substrate into a furnace at a high temperature and annealing the semiconductor substrate flowing a nitride gas into the furnace at about 20 l/min, and filling an insulator in the trench.
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Mazumder et al Improved Reliability of No Treated NH3-Nitrided Oxide with Regard to O2 Annealing Solid State Electronics vol. 42 No. 6 pp. 921-924 1998.*
T. S. Chao et al., “Mechanism of Nitrogen Coimplant for Suppressing Boron Penetration in &rgr;+-polycrystalline Silicon Gate of &rgr; Metal-Oxide Semiconductor Field Effect Transistor”,Appl. Phys. Letters, vol. 69, No. 12, Sep. 16, 1996, pp. 1781-1782.
Genshu Fuse et al., “A New
Blum David S
Bowers Charles
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