Improving memory layout based on connectivity considerations

Details Improving memory layout based on connectivity considerations Improving memory layout based on connectivity considerations

1996-10-07

1998-07-28

Cosimano, Edward R.

395705, 395707, 395708, 395709, G06F 945

Patent

active

057872848

ABSTRACT:
A technique used during interprocedural compilation in which program objects are grouped together based on the weights of the connections between the objects and their costs. System-imposed constraints on memory size can be taken into account to avoid creating groupings that overload the system's capacity. The groupings can be distributed over memories located on different processors.

REFERENCES:
patent: 5107418 (1992-04-01), Cramer et al.
patent: 5193190 (1993-03-01), Janczyn
patent: 5367683 (1994-11-01), Brett
patent: 5428793 (1995-06-01), Odnert et al.
patent: 5485616 (1996-01-01), Burke et al.
patent: 5530866 (1996-06-01), Koblenz et al.
patent: 5555417 (1996-09-01), Odnert et al.
patent: 5579520 (1996-11-01), Bennett
patent: 5606697 (1997-02-01), Ono
Chow, "Minimizing register usage penalty at procedure calls", Proc. of the SIGPLAN, '88 Conf. on Programming Language Design & Implementation, pp. 85-94, Jul. 1988.
Wall, "Global register allocation at link time", Proc. of the SIGPLAN, SIGPLAN notices, vol. 21, No. 7, pp. 264-275, Jul. 1986.
Lomet, "Data flow analysis in the presence of procedure calls", IBM Research & Development, USA, vol. 21, No. 6, pp. 559-571, Nov. 1977.
Hwu et al. "Checkpoint repair for high-performance out-of-order execution machines", IEEE Trans. on Computers, vol. C-36, No. 12, pp. 1496-1514, Dec. 1987.
Cooper et al. "Impact of interprocedural analysis and optimization in the R.sub.n programming environment." ACM Trans. Programming Language & Syst., vol. 8, No. 4, pp. 491-523, Oct. 1986.
Richardson, "Code optimization across procedures", IEEE Comput. Soc., vol. 22, No. 2, pp. 42-50, Feb. 1989.
K.M. Gilbert, Effective Register Management During Code Generation, IBM Technical Disclosure Bulletin, vol. 15, No. 8, Jan. 1973, pp. 2640-2645.
K. O'Brien et al, Advanced compiler Technology for the RISC System/6000 Architecture, IBM RISC System/6000 Technology, pp. 154-161, 1990.

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