Improved method for accessing machine state information

Details Improved method for accessing machine state information Improved method for accessing machine state information

1992-10-20

1995-04-04

Kriess, Kevin A.

Excavating

364DIG2, 3649218, 364949, 371 161, 371 225, 395700, G01R 3128

Patent

active

054045266

ABSTRACT:
A method is provided for overcoming the slow speed of accessing machine state information from a device under test using boundary scan technology. The method minimizes the total number of words sent over the lengthy communications path by filtering out intermediary data. The method enables transfers of results to take place while other boundary scan circuitry commands are executing. Firmware is provided that transforms a boundary scan circuitry controller into a debug controller. Building the debug functions into the system makes it possible to have debug capability from module level integration all the way to system level integration.

REFERENCES:
patent: 5155732 (1992-10-01), Jarwala et al.
Lester, et al.; "Implementing JTAG Boundary Scan with Methodologies which Minimize Design Overhead"; Apple Computer, Inc.; 1989.
Parker; "The Impact of Boundary Scan on Board Test", Hewlett-Packard; 1989.
Andrews; "JTAG works to standardize chip, board and system self-test", Computer Design; 1989 Jul.
Goering; "Boundary-scan technique target board-level testability"; Computer Design; 1987 Oct.
Donlin; "Software generates test patterns for boundary-scan boards"; Computer Design, 1991 Nov.
Breuer, Melvin, et al.; "A Test and Maintenance Controller for a Module Containing Testable Chips"; University of S. California; 1988.

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