Improved current mirror biasing arrangement for integrated circu

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307495, 323315, 330257, 330288, 330300, H03F 3345, H03F 316, H03L 500

Patent

active

044503660

ABSTRACT:
A current mirror biasing arrangement for an electronic circuit, particularly one intended for an integrated circuit employs a current mirror constituted by series connected pnp and npn transistors having their collectors connected together. A pair of series-connected field effect transistors (FET) connected between a voltage source and ground have their gates connected to the emitter and collector of the pnp transistor and their junction to the pnp transistor base. The pnp transistors to be biased have their bases connected to the said FET junction. The gate current of the operative FET can be made negligible so that substantially perfect matching is obtained between the npn transistor current and the "mirror" biasing current. Preferably the FET are of subsurface junction type, their low pinch-off voltage and low gate current making them particularly suitable for low voltage application.

REFERENCES:
patent: 3875430 (1975-04-01), Prak
patent: 4066917 (1978-01-01), Compton et al.
patent: 4176368 (1979-11-01), Compton
patent: 4207537 (1980-06-01), Cave et al.
patent: 4276515 (1981-06-01), Nishimoto

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