Improper writing prevention circuit and a memory device and a da

Details Improper writing prevention circuit and a memory device and a da Improper writing prevention circuit and a memory device and a da

1990-12-20

1993-05-18

Beausoliel, Jr., Robert W.

Excavating

365201, G11C 2900

Patent

active

052126943

ABSTRACT:
An improper writing prevention circuit having a source voltage detection circuit which detects the value of a source voltage and generates a first control signal to be sent to a state selection terminal of a memory device, a reference register in which a predetermined reference data is stored in advance, a first writing test register to and from which data can be written and read for receiving data to be referred to through a data bus, a validity check circuit for writing test which determines consistency of the reference data with the data to be referred to and generates a second control signal on the basis of the above determination, and a state selection circuit which generates a state selection signal to be applied to the state selection terminal in accordance with the first and second control signals. Improper writing operation to the memory can be prevented by changing its state from an active state to a non-active state by the state selection signal.

REFERENCES:
patent: 3751649 (1973-08-01), Hart, Jr.
patent: 4775857 (1988-10-01), Staggs
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 5053698 (1991-10-01), Ueda
patent: 5109382 (1992-04-01), Fukunaka

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