Improper bit combination detection circuit

Details Improper bit combination detection circuit Improper bit combination detection circuit

1988-12-19

1990-12-11

Atkinson, Charles E.

Excavating

36443104, G06F 1100

Patent

active

049775596

ABSTRACT:
Combinational logic circuits are used with a temporary storage device holding data bytes to detect improper bits in both the lower and upper nibbles of the bytes. Combinations of bit patterns derived from both nibbles permit flagging the occurrences of a variety of bit errors existing in sequentially transmitted parallel data bytes.

REFERENCES:
patent: 4059749 (1977-11-01), Feilchenfeld
patent: 4312071 (1982-01-01), Bloch
patent: 4835776 (1989-05-01), Annamalai

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