Implicit tree-mapping technique

Details Implicit tree-mapping technique Implicit tree-mapping technique

1995-11-01

1998-09-01

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

058019570

ABSTRACT:
A method for translating a boolean function into a logic circuit using gates from a standard library is provided. The method includes the steps of translating the boolean function into a network comprising a plurality of sub-trees, where each of the sub-trees represents a portion of the function, and where each sub-tree includes a plurality of representations for that portion of the function. The plurality of representations are stored in an alterative logic diagram, which comprises a plurality of ugates. The ugates are data structures which define the inputs and the connectivity of the respective ugate in the sub-tree. The sub-tree is mapped to gates from the standard library by selecting the best sub-tree representation. Accordingly, an improved method of logic synthesis is provided that allows for the optimal representation to be provided by starting with a wider range of inputs to the mapping process.

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