Implementing vector memory operations

Details Implementing vector memory operations Implementing vector memory operations

2005-10-21

2009-12-01

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

C712S024000

Reexamination Certificate

active

07627735

ABSTRACT:
In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.

REFERENCES:
patent: 5184320 (1993-02-01), Dye
patent: 6336168 (2002-01-01), Frederick et al.
patent: 2004/0064670 (2004-04-01), Lancaster et al.
patent: 2006/0095717 (2006-05-01), Glossner et al.
“Tarantula: A Vector Extension to the Alpha Architecture” Espasa, et al. ACM SIGARCH Computer Architecture News. vol. 30, Issue 2. Session 8: Vector architecture. pp. 281-292. May 2002.

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