Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
1999-08-30
2002-12-03
Nappi, Robert E. (Department: 2838)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C257S738000, C257S788000, C438S613000
Reexamination Certificate
active
06489557
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field Of The Invention
This invention relates to a package for an integrated circuit. More particularly, the present invention relates to a method of implementing micro BGA™.
2. Description Of Related Art
As semiconductor devices become more and more complex, electronics designers are challenged to fully harness their computing power. Some of today's products can feature millions of transistors and device count is expected to continue increasing in the future. With a greater number of functions integrated on a die or chip of silicon, manufacturers and users face new and increasingly challenging electrical interconnect issues. To tap the power of the die efficiently, each level of electrical interconnect from the die to the functional hardware or equipment must also keep pace with these revolutionary devices.
Today, sub-micron feature size at the die level is driving package feature size down to the design rule level of the early silicon transistors. At the same time, electronic equipment designers are shrinking their products, increasing complexity, and setting higher expectations for performance. In order to meet these demands, package technology must deliver higher lead counts, reduced pitch, reduced footprint area, and significant overall volume reduction. Package technology has responded to these challenges with a number of concept changes and improvements. For instance, in response to the need for increasing number of leads or pins required for packages, ball grid array interconnects have been used to increase the density of contacts. This approach has not only helped to control package size, but also to enhance electrical performance by reducing trace length.
Integrated circuits (IC) are typically housed within a package that is mounted to a printed circuit board. The package has conductive leads or pins that are soldered to the printed circuit board and coupled to the integrated circuit by a lead frame. One kind of package commonly referred to as a ball grid array (BGA) is an integrated circuit package which has a plurality of solder balls that interconnect the package to a printed circuit board. The solder balls are attached to a polyimide based flexible circuit board which has a number of conductive traces and accompanying solder pads. The integrated circuit die is connected to the solder pads of the flexible circuit by wire bonds and electrically coupled to the solder balls through conductive traces routed across the flexible circuit.
However, customers in applications such as handheld communications such as cellular phones, Personal Communications Service (PCS) pagers, computing, PCMCIA (Personal Computer Memory Card International Association) I/O cards, and other small form factor system have different miniaturization goals and needs. Fit, form, and function tend to be market specific. In addition, IC manufacturers have recognized that existing surface-mount packages such as the Thin Small Outline Package (TSOP) do not take full advantage of the semiconductor process lithography improvements that were driving smaller integrated circuit die sizes. The die cost typically has the most impact on the total manufacturing cost. In order to drive down the cost of the final product, semiconductor manufacturers continually migrate to state-of-the-art processes to reduce die size.
Another type of integrated circuit package is the micro ball grid array™ (&mgr;BGA™) package. &mgr;BGA is a registered trademark of Tessera, Inc. of San Jose, Calif. The &mgr;BGA package enables IC manufactures to respond to customer needs for smaller and thinner components. The &mgr;BGA package is considered a chip size package (CSP). A chip size package is generally defined as a package which does not exceed the die size by greater than 20%. However, the &mgr;BGA package does not allow a smaller die to be placed in the same package without affecting package dimensions. Hence, smaller die generally result in a smaller &mgr;BGA package and usually a finer ball pitch.
Since the package size and pitch change with die size, semiconductor manufacturers and customers may need to retool handling and testing equipment each time the die size changes due to die shrinks. Furthermore, the smaller solder ball pitch may require more complicated and expensive printed circuit board technologies and surface mount technologies.
Hence it would therefore be desirable to have a package and method for producing a &mgr;BGA package which has a uniform size regardless of the size of the die contained in the package.
SUMMARY OF THE INVENTION
The present invention introduces a method of implementing micro BGA. More specifically, the present invention discloses a method of packaging an integrated circuit into an integrated circuit assembly. The method of the present invention first mounts polyimide tape to a lead frame. The polyimide tape serves as a substrate for the integrated circuit package. Next, a piece of elastomer is coupled to said polyimide tape. Then an integrated circuit die is attached to said elastomer. Lead beams are then bonded from bond pads on said die to said lead frame. Solder balls are attached to said lead frame. The attached solder balls may be located beyond the area of said die.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
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Eskildsen Steven R.
Foehringer Richard B.
Kaller Deborah S.
Intel Corporation
Lam Peter
Laxton Gary L.
Nappi Robert E.
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