Implementing mass storage device functions using host processor

Details Implementing mass storage device functions using host processor Implementing mass storage device functions using host processor

1996-03-28

1998-09-01

Canney, Vincent P.

Excavating

39518206, G06F 1100

Patent

active

058020691

ABSTRACT:
A computer system comprises a host processor, host memory, and a mass storage device interconnected via a high-speed data bus. An operating system and a driver for the mass storage device are implemented on the host processor. The mass storage device is capable of being connected to the computer system via the data bus, such that a portion of the host memory is allocated for use by the mass storage device; the mass storage device uses the host memory portion for one or more particular mass storage device operations; and the operating system and the driver are unaware of how the mass storage device uses the host memory portion. In a preferred embodiment, the mass storage device requests and the host processor allocates a portion of host memory for exclusive use by the mass storage device to perform such functions as predictive failure analysis, maintenance of deallocated sector lists, and data prefetching.

REFERENCES:
patent: 5257367 (1993-10-01), Goodlander et al.
"P1394 IEEE Draft Standard for a High Performance Serial Bus," by IEEE, P1394, D8.Ov2, Jul. 1995, DS3285, pp. 1-384.

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