Implementations of AES algorithm for reducing hardware with...

Cryptography – Particular algorithmic function encoding

Reexamination Certificate

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C380S029000, C380S037000

Reexamination Certificate

active

07809132

ABSTRACT:
An AES encryption processor is provided for reducing hardware with improved throughput. The processor is composed of a selector unit selecting an element of a state in response to row and column indices, a S-box for obtaining a substitution value with said selected element used as an index, a coefficient table providing first to fourth coefficients in response to said row index, first to fourth Galois field multiplexers respectively computing first to fourth products, which are obtained by multiplication of said substitution value with first to fourth coefficients, respectively, and an accumulator which accumulates the first to fourth products to develop first to fourth elements of a designated column of a resultant state.

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H. Seike et al., “Trial product of the AES cryptography using FPGA”, The Institute of Electronics, Information and Communication Engineers, Technical Report of IEICE, VLD2001-91, ICD2001-136, FTS2001-38, Nov. 2001.
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Implementations of AES (Rijndael) in C/C++ and Assembler, “Aescrypt.asm”, Jan. 21, 2003, pp. 1-11.

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