Implementation of quantization for SIMD architecture

Details Implementation of quantization for SIMD architecture Implementation of quantization for SIMD architecture

2005-02-01

2005-02-01

Diep, Nhon (Department: 2613)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

Reexamination Certificate

active

06850566

ABSTRACT:
A system for improving the speed of the video encoding process by decreasing the number of cycles to perform the quantization. The disclosed system achieves the improvement through use of parallel processor such as one having a Single Instruction, Multiple Data (SIMD) architecture. Concurrent processing during one instruction cycle is accomplished, thereby leading overall to the use of fewer instruction cycles. In the preferred embodiment, an MMX instruction set is used for executing four quantization in parallel. The disclosed system also achieves a higher precision of the quantization during the encoding of video signals with the SIMD architecture by using a larger multiplier and larger shift factor.

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