Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-04-27
2001-04-17
Olms, Douglas (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S429000
Reexamination Certificate
active
06219351
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to implementation of buffering in a packet-switched telecommunications network, particularly in an ATM network wherein the packets to be transferred have a constant length.
BACKGROUND OF THE INVENTION
To aid the understanding of the following description, some terms to be used later will first be defined.
A switching matrix is comprised of a plurality of switching elements which are generally identical and are interconnected according to a given topology. In the literature of the art, such a switching matrix may also be called a “switching network”, since the switching elements form a network having the given topology. Hence, a switching matrix is considered to have a defined form when its switching elements and their interconnections are known.
Switching elements may be treated as the elementary “building blocks” from which the switching matrix is constructed by connecting a plurality of similar switching elements into a network.
The term switch is used to denote the entity configured about a switching matrix. Hence, a switch can denote any means employed for signal switching in a communications network. In the present context, a switch is a packet switch as the invention is related to buffering in a packet-switched telecommunications network, particularly in an ATM network.
ATM (Asynchronous Transfer Mode) is a connection-oriented packet-switching technique, which has been selected by the international organization for telecommunications standardization, ITU-T, as the target transfer mode solution for implementing a broadband multimedia network (B-ISDN). In an ATM network, the problems of conventional packet-switched networks (such as X.25 networks) are overcome by transmitting short packets of a constant length (53 bytes) called cells. Each cell comprises a 48-byte payload portion and a 5-byte header. Further discussion of an ATM network herein will be omitted as non-essential subject to the understanding of the invention. When required, a closer description of this topic can be found in international standards and textbooks of the art.
FIG. 1
shows schematically an ATM switch seen from the outside. The switch has n input ports I
1
. . . I
n
and m output ports O
1
. . . O
m
. A cell stream CS is present at each port of the ATM switch
11
. The header of an individual cell in the data stream is denoted by symbol HD. In the ATM switch, the cells are switched from the input port I
i
to the output port O
j
, and simultaneously the value of the cell header is translated from an incoming value to an outgoing value. For this purpose, the switch includes a translation table
12
by means of which said header translation is made. From the table can be seen that, for example, all the cells received at input port I
1
, and having a header with a value X are switched onto output port O
1
, whereby the header of the outgoing cells is simultaneously given the value K. Cells present on different input ports may have headers of equal value; for example, cells received at input port I
n
with the same header value X are also switched onto output port O
1
, but their header is given the value J on the output port.
Hence, the main tasks of a switch are: state switching (switching from the input port to the desired output port, i.e. routing) and “header switching”, that is, header translation. Occasionally, as is also evident from the figure, two cells may be simultaneously contending for access onto the same output port. For this purpose, the switch must have buffering capacity to avoid the necessity of discarding cells in such a situation. Hence, the third main task of a switch is to provide buffering.
The present invention specifically relates to implementation of buffering. Since the invention is intended for an ATM network in particular, the method will be applied primarily in the switching elements of an ATM switch.
Traffic sources generating both constant bit rate (CBR) data and variable bit rate (VBR) data can be connected to an ATM network. The ATM network causes cell delay variation (CDV) on cells passed via these connections. In the case of variable-rate traffic sources in particular, a high delay variation poses synchronizing problems at the receiver. In other words, the original rate variation at the receiving end is very difficult to determine after the network has caused delay variations on the transmitted signal. Equalization of excessive rate variations also requires a high buffering capacity at the receiver.
The known methods for equalizing ATM network-induced delay variations are mainly based on applying delay priorities. The connections are classified into different classes according to their CDV requirements, and dedicated buffers are reserved for connections with stringent CDV requirements. Such buffers have a higher priority than those for other connections, which means that all cells on such buffers are forwarded before cells on any lower-priority buffer are sent. Hence, the first cell on a lower-priority buffer will not be forwarded until the higher-priority buffer is empty.
One drawback of the above known solutions is that the hardware configuration will be the more complex the greater the number of parallel buffers. This drawback is highlighted particularly when the switch comprises a plurality of switching stages, which likewise results in a high number of switching elements and buffers.
SUMMARY OF THE INVENTION
It is an object of the present invention to eliminate the drawbacks described above and to provide a solution wherewith the delay variation can be maintained within desired limits with a very simple buffering arrangement.
This object is achieved with a solution as defined in the independent claims.
The idea of the invention is to utilize a FIFO-type buffer through which “normal traffic” (i.e., traffic not critical with respect to delay variations) is fed through on the conventional FIFO principle. In addition to this “normal traffic”, part of the traffic is classified as critical with respect to delay variations. For each of such classes, there is a dedicated feed point at a given location at the centre of the buffer, to which the incoming cell is fed as far as possible. Hence, the idea is to feed in each case a cell of a given class as close to a predetermined fixed point in the buffer queue as possible, regardless of how many memory locations will possibly remain empty between the cell to be fed to said point and the current last cell in the queue.
On account of the solution of the invention, the buffer is simple to manage, as after the cell has been written into the buffer, the buffer operates as a conventional FIFO buffer. Thus, the reading mechanism is as simple as possible; a cell is read out from the memory location at the head of the queue in each outbound time slot, and the stored data units are moved forward towards the memory location at the head of the queue after each individual reading operation.
In accordance with the preferred embodiment of the invention, the buffering is implemented on the output of the ATM switching element, and the buffer only utilizes two traffic classes: “normal traffic” that is not critical with respect to delay variations, and a class defined as critical with respect to delay variations. “Normal traffic” utilizes the buffer on the FIFO principle, that is, a cell is stored in each case in the first empty memory location starting from the head of the queue.
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Altera Law Group LLC
Nokia Telecommunications Oy
Olms Douglas
Pizarro Ricardo M.
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