Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-02-06
2003-12-09
Le, Thong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S185240
Reexamination Certificate
active
06661711
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to mass digital data storage systems. More particularly, the present invention relates to systems and methods for tightening the erased bit threshold voltage distribution associated with a sector to effectively improve the performance of read operations associated with the sector.
2. Description of the Related Art
The use of non-volatile memory systems such as flash memory storage systems is increasing due to the compact physical size of such memory systems, and the ability for non-volatile memory to be repetitively reprogrammed. The compact physical size of flash memory storage systems facilitates the use of such storage systems in devices which are becoming increasingly prevalent. Devices which use flash memory storage systems include, but are not limited to, digital cameras, digital camcorders, digital music players, handheld personal computers, and global positioning devices. The ability to repetitively reprogram non-volatile memory included in flash memory storage systems enables flash memory storage systems to be used and reused.
Flash memory storage systems generally include flash memory cells. A flash memory cell may include a transistor with a source and a drain that are formed in a silicon substrate, or a flash memory cell may include a source and a drain that are formed in a well within a silicon substrate. Hence, sectors associated with a flash memory card generally include multiple transistors. When a flash memory cell is programmed, a relatively large voltage may be applied to a drain while a source is grounded, and a larger voltage may be applied to a control gate to raise the voltage potential of a floating gate, as will be understood by those skilled in the art. Programming a memory cell generally involves substantially injecting electrons into a floating gate to create a desired threshold voltage for the memory cell. A desired threshold voltage may be considered to be a voltage that is applied to the control gate of the memory cell to allow conduction to occur through a channel region during a read operation.
A cell that is programmed may be erased. When multiple cells or bits within a sector are erased, a distribution of the bits may be created.
FIG. 1
a is a diagrammatic representation of a plot of an erased bit threshold voltage distribution associated with a sector of a memory card. A plot
110
includes an axis
112
which represents a number of bits and an axis
114
which represents the threshold voltage (V
T
) associated with a sector or, more specifically, of transistors associated with the sector. An erased bit threshold voltage distribution
116
indicates the disposition of cells or bits associated with a sector or a block. It should be appreciated that the shape of distribution
116
may vary widely and, for purposes of illustration, has been exaggerated. Bits that are most erased or over-erased are reflected in a trailing edge
118
, while bits that are least erased are reflected in a leading edge
120
.
An erase verify level (ERV
1
)
122
is generally defined such that preferably all bits in distribution
116
fall below ERV
1
122
. Typically, ERV
1
122
may be set at a negative voltage level, e.g., approximately −0.8 Volts (V), that enables a margin
124
between ERV
1
122
and a read level
126
to be maintained. When any bit exceeds read level
126
, that bit will generally be read.
When most erased bits, or bits at trailing edge
118
of distribution
116
, are too negative, the performance of the overall memory device which includes the sector associated with the bits may be compromised. As will be appreciated by those skilled in the art, most erased or over-erased bits are often associated with transistors which have a relatively low voltage level, e.g., a voltage level of approximately −3.0 V or less. When the voltage level of a transistor is too low, current may be conducted through the transistor. By way of example, leakage currents may flow through the transistor as a result of floating gates associated with the transistors substantially losing electrons. When current is conducted through the transistor due to a voltage that is very negative, the sensing and programming associated with the sector may occur less efficiently. Over-erased or most erased bits also generally take longer to erase than other bits and, as a result, substantially define the erase time associated with substantially all bits of the sector
To correct for the most erased bits, distribution
116
may effectively be shifted through the use of a process such as soft programming. Soft programming, as will be appreciated by those skilled in the art, generally involves applying a voltage which effectively shifts most erased bits to a higher voltage level. During soft programming, a relatively high voltage may be provided to a transistor which effectively causes electrons to be pulled onto the floating gate associated with the transistor. In other words, electrons may effectively be injected into the floating gate.
When most erased bits are corrected using soft programming, least erased bits, or bits associated with leading edge
120
of distribution
116
are affected. Specifically, distribution
116
is shifted such that most erased bits and least erased bits are substantially all less negative. As shown in
FIG. 1
b
, distribution
116
may shift such that after a soft program, distribution
116
becomes shifted distribution
116
′. For purposes of illustration, the amount by which distribution
116
shifts to become shifted distribution
116
′ has been exaggerated. Typically, a soft program will be stopped when a certain number of bits have exceeded ERV
1
122
. That is, when the number of “failing bits” exceeds a threshold, soft programming is generally stopped. If a certain number of bits have exceeded ERV
1
122
, and there are still most erased bits that are considered to be too negative, then an erase procedure on the sector which includes the bits may be performed again.
If margin
124
is exceeded by leading edge
120
′ of distribution
116
′, some least erased bits may exceed read level
126
and, hence be read during a read operation. Since any least erased bit that is read during a read operation will generally cause a failure of a bit during a read operation, an error correction code (ECC) circuit associated with the memory card may correct for the failure. Although the ECC circuit may correct for the least erased bit that exceeds read level
126
, the correction of the least erased bit generally takes away from the bandwidth associated with the ECC circuit. For example, in many memory cards, an ECC circuit may be capable of only correcting for four total bits. As such, the correction of the least erased bit that exceeds read level
126
reduces the number of bits read in a read operation which may be corrected to three.
In order to reduce the likelihood that least erased bits exceed read level
126
, a second erase verify level (ERV
2
) may be implemented to enable a least erased bit to be identified before the least erased bit exceeds read level
126
. As shown in
FIG. 1
c
, an ERV
2
140
is typically set such that ERV
2
140
is within margin
124
such that a new margin
144
may be defined by ERV
1
122
and ERV
2
140
. That is, ERV
2
140
may have a higher voltage than ERV
1
122
, and a lower voltage than read level
126
. New margin
144
may be selected to meet an erase speed requirement such that if no least erased bits exceed ERV
2
140
, the erase speed associated with the sector is considered to be acceptable. In addition, of no least erased bits exceed ERV
2
140
, then the least erased bits may all still be read as erased bits, and not as read bits.
A certain number of bits may be allowed to exceed ERV
1
122
, and a subset of the bits which exceed ERV
1
122
may be allowed to exceed ERV
2
140
before a new erase operation is performed. For example, up to eight total bits may be allowed to exceed ERV
1
122
, with one of
Pan Feng
Yu Tat-Kwan Edgar
Le Thong
Sandisk Corporation
LandOfFree
Implementation of an inhibit during soft programming to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Implementation of an inhibit during soft programming to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Implementation of an inhibit during soft programming to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3165953