Implementation of a digital decimation filter and method

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G06F 1710

Patent

active

057516154

ABSTRACT:
The present invention is for an implementation of a multi-stage digital decimation filter and a method of decimating a multi-bit input signal, where n/2 additions are performed, where n=the number of bits in each filter coefficient. A compensation stage is also provided. Scaling and multiplication of data with coefficients is performed using a common architecture to the Decim. 2 and Decim. 3 stages. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.

REFERENCES:
patent: 4590457 (1986-05-01), Amir
patent: 4704600 (1987-11-01), Uchimura et al.
patent: 4849662 (1989-07-01), Holberg et al.
patent: 4851841 (1989-07-01), Sooch
patent: 4876542 (1989-10-01), van Bavel et al.
patent: 4918454 (1990-04-01), Early et al.
patent: 4920544 (1990-04-01), Endo et al.
patent: 4939516 (1990-07-01), Early
patent: 5027306 (1991-06-01), Dattorro et al.
patent: 5039989 (1991-08-01), Welland et al.
patent: 5055843 (1991-10-01), Ferguson, Jr. et al.
patent: 5061928 (1991-10-01), Karema
patent: 5065157 (1991-11-01), Ribner et al.
patent: 5068660 (1991-11-01), Swanson et al.
patent: 5079550 (1992-01-01), Sooch et al.
patent: 5084702 (1992-01-01), Ribner
patent: 5103229 (1992-04-01), Ribner
patent: 5148166 (1992-09-01), Ribner
patent: 5148167 (1992-09-01), Ribner
patent: 5153593 (1992-10-01), Walden et al.
patent: 5157395 (1992-10-01), Del Signore et al.
patent: 5162799 (1992-11-01), Tanimoto
patent: 5184130 (1993-02-01), Mangelsdorf
patent: 5189419 (1993-02-01), Lyden
patent: 5198817 (1993-03-01), Walden et al.
patent: 5208597 (1993-05-01), Early et al.
patent: 5210537 (1993-05-01), Mangelsdorf
patent: 5274375 (1993-12-01), Thompson
patent: 5283578 (1994-02-01), Ribner et al.
patent: 5298900 (1994-03-01), Mauthe et al.
patent: 5311181 (1994-05-01), Ferguson, Jr. et al.
patent: 5590065 (1996-12-01), Lin
patent: 5617344 (1997-04-01), Young et al.
"A 16-Bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping," Matsuya, et al., IEEE Journal of Solid State Circuits, vol. SC-22, No. 6, pp. 921-929, Dec. 1987.
"A Third-Order Multistate Sigma-Delta Modulator with Reduced Sensitivity to Nonidealities," Ribner, et al., IEEE Journal of Solid-State circuits, vol. 26, No. 12, pp. 1764-1774, Dec. 1991.
"A Higher Order Topology for Interpolative Modulators for Oversampling A/D Converters," Chao, et al., IEEE Transactions on Circuits and Systems, vol. 37, No. 3, pp. 309-318, Mar. 1990.
"A Self-Calibrating 15 Bit CMOS A/D Converter," Hae-Seung Lee et al.; IEEE Journal of Solid State Circuits, vol. SC-19, No. 6, Dec. 1984.
"A 12-Bit Successive-Approximation-Type ADC with Digital Error Correction," Kanit Bacrania, IEEE Journal of Solid-State Circuits, vol. SC-21, No. 6, Dec. 1986.
"A Third-Order Cascaded Sigma-Delta Modulators," Louis A. Williams III et al., IEEE Transactions on Circuits and Systems, 38 (1991) May, No. 5, New York, pp. 489-497.
"Low-Distortion Switched-Capacitor Filter Design Techniques," Kuang-Lu Lee, et al., IEEE Journal of Solid-State Circuits, vol. SC-20, No. 6, Dec. 1985, pp. 1103-1113.
"The Implementation of Digital Echo Cancellation in Codecs," Vladimir Friedman, et al., IEEE Journal of Solid-State Circuits, vol. 25, No. 4, Aug. 1990, pp. 979-986.
"A 192ks/s Sigma-Delta ADC with Integrated Decimation Filters Providing -97.4dB THD," Mark A. Alexander, et al., ISSCC94/Session 11/Oversampled Data Coversion/Paper TP 11.3, 1994 IEEE International Solid-State Circuits Conference.
"A Voiceband Codec with Digital Filtering," James C. Candy, et al., IEEE Transaction on Communications, vol. COM-29, No. 6, Jun. 1981, pp. 815-829.
"A Per-Channel A/D Converter Having 15-Segment .mu.-255 Companding," James C. Candy, et al., IEEE Transactions on Communications, vol. COM-24, Jan. 1976.
"Switched-Capacitor Second-Order Noise-Shaping Coder," G. Lainey, et al., Electronics Letters, 17th Feb. 1983, vo. 19, No. 4, pp. 149-150.
"Multirate Filter Designs Using Comb Filters," Shuni Chu, et al., IEEE Transactions on Circuits and Systems, vol. CAS-31, No. 11, Nov. 1984, pp. 913-924.
"A 120dB Linear Switched-Capacitor Delta-Sigma Modulator," Donald A. Kerth, et al., 1994 IEEE International Solid-State Circuits Donference, Digest of Technical Papers, TP 11.6, pp. 196-197, IDDCC94/Thursday, Feb. 17, 1994/Sea Cliff.
"A Stereo 97dB SNR Audio Sigma-Delta ADC," Tapani Ritoniemi, et al., 1994 IEEE International Solid-State Circuits Conference, ISSCC94/Session 11/Oversampled Data Conversion/Paper TP 11.7, pp. 198-199.
"A Digitally-Corrected 10b Delta-Sigma Modulator," Charles D. Thompson, et al., 1994 IEEE International Solid-State Circuits Conference, ISSCC94/Session 11/Oversampled Data Conversion/Paper TP 11.5, pp. 194-195.
"An Economical Class of Digital Filters for Decimation and Interpolation," Eugene B. Hogenauer., IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-29, No. 2, Apr. 1981, pp. 155-162.
"Decimation for Sigma Delta Modulation," James C. Candy, IEEE Transactions on Communications, vol. COM-34, No. 1, Jan. 1986, pp. 72-76.
"Multirate Digital Filters, Filter Banks, Polyphase Networks, and Applications: A Tutorial," P. P. Vaidyanathan, Proceedings of the IEEE, vol. 78, No. 1, Jan. 1990, pp. 56-93.
"A Multistage Delta-Sigma Modulator without Double Integration Loop," Toshio Hayashi, et al., 1986 IEEE International Solid-State Circuits Conference, ISSCC 86/Thursday, Feb. 20, 1986/California Pavilion C, pp. 182-183.
"Circuit and Technology Consideration for MOS Delta-Sigma A/D Converter," Max W. Hauser et al., 1986 IEEE, pp. 1310-1315.
"A 16b Oversampling A/D Conversion Technology using Triple Integration Noise Shaping," Yasuyuki Matsuya, et al., 1987 IEEE International Solid-State Circuits Conference, ISSCC 87/Wednesday, Feb. 25, 1987/Trianon Ballroom, pp. 48-50.
"A 3-.mu.m CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting," Paul Defraeye, et al., IEEE Journal of Solid-State Circuits, vol. SC-20, No. 3, Jun. 1985, pp. 679-687.
"Fourth Order Sigma-Delta Modulator Circuit For Cigital Audio and ISDN Applications," T. Karema, et al., Tampere University of Technology, Finland, pp. 223-227.
"Area-Efficient Multichannel Oversampled PCM Voice-Band Coder," Bosco H. Leung, et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 6, Dec. 1988, pp. 1351-1357.
"Design and Implementation of Digital FIR Filters" P. P. Vaidyanathan, Chapter 2 in Handbook of DSP Engineering Applications, D. F. Elliott, editor, Academic Press, 1987.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Implementation of a digital decimation filter and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Implementation of a digital decimation filter and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Implementation of a digital decimation filter and method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-989234

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.