Implementation method of digital phase-locked loop

Details Implementation method of digital phase-locked loop Implementation method of digital phase-locked loop

2001-11-21

2004-11-02

Hudspeth, David (Department: 2651)

Dynamic magnetic information storage or retrieval

Automatic control of a recorder mechanism

Controlling the head

C360S046000

Reexamination Certificate

active

06813111

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to digital systems and, more particularly, to a method and apparatus for incrementally adjusting the phase of a digital signal.
BACKGROUND OF THE INVENTION
Computers and other digital electronic products generally include semiconductor integrated circuits. Present-day integrated circuits may contain millions of transistors and be configured, for example, as a central processing unit (CPU), arithmetic logic unit (ALU), random access memory (RAM), programmable logic array (PLA), application specific integrated circuit (ASIC), or digital signal processor (DSP). Both the sophistication and speed of operation of these integrated circuits has rapidly increased because of improvements in integrated circuit manufacturing technologies resulting in smaller and faster devices.
Digital systems, having these semiconductor integrated circuits, have digital signals such as clock signals to process data, control circuit timing and setup, and for data communication synchronization. A clock signal has a period waveform and normally has a constant frequency. Clock signals or “clocks” may be used throughout a digital system including many integrated circuits. A very large integrated circuit may have multiple clock circuits that drive various circuits therein. These multiple clock circuits may be used for ease in clock signal distribution within the integrated circuit or for specific circuit functions requiring isolated or controllable clock signals.
Clock distribution within an integrated circuit requires precise phase correlation. This is to insure that there is proper setup and processing of the digital information within the integrated circuit. The timing requirements of multiple integrated circuits of a digital system also require equally precise phase correlation. Reliable operation of the integrated circuit depends upon data being stable when a clock signal is received. If a clock signal is out of phase, then the data may no longer be valid. This is also true when transferring signals between multiple integrated circuits.
A typical read channel includes the data head, preconditioning logic (such as preamplification circuitry and filtering circuitry), a data detector and recovery circuit, and error detection and correction circuitry. The read channel is typically implemented in a drive controller associated with the disk drive.
Digital phase-locked loops (DPLL) are typically adopted for magnetic recording channels to accurately extract sampling time for digital signal processing. Typically, the DPLL operates in two different modes, phase and frequency lock-in (acquisition mode) for determining the preamble of data, and tracking slow phase and frequency variation of the incoming signal (tracking mode) to process user data prerecorded on the disk. Most disk drive applications require a fast acquisition mode. In order to achieve this, a known data sequence, referred to as a preamble, can be recorded on the magnetic medium for this fast acquisition mode.
A second order digital PLL is shown in
FIG. 1. A
phase error detector (PED)
100
estimates the timing phase error of the sampled signal when used in conjunction with the preamble in the acquisition mode or estimates the timing phase error from decisions from a channel symbol detector
102
in the tracking mode. A first order loop filter
104
, which results in the second order loop, has two variable parameters, namely the proportional (k
p
) and the integral (k
i
) path gains. These proportional and integral gains control the tracking capability of the loop to phase variation of the incoming signal. This is based on the concept that known signals can be processed faster than unknown signals. The voltage controlled oscillator (VCO)
106
is implemented by an accumulator. The sampler phase is updated according to the VCO output and illustrated as a switch
108
.
In the acquisition mode, large gains for the low-pass filter are used for fast phase/frequency lock-in. In contrast, in the tracking mode, smaller gains are used for tracking rather slow variations in the phase and frequency of incoming signals. If a single low-frequency filter is implemented in hardware for both acquisition and tracking modes, which of course uses only one set of gain values, gain resolution, which is the number of different gain values to be set, should be increased. This increase in gain resolution correspondingly requires bit resolution to be changed. The required bit resolution for implementation would also be different for the two modes. The low-pass filter would require a large number of bits for each signal representation in order to effectively achieve high resolution. However, as a result, this implementation with high resolution of a low-pass filter may slow the hardware down by increasing the length of the signal critical path. As signal speeds increase for high-speed applications, this level of complexity and corresponding increase in processing time effectively restricts the speed and limits the application.
SUMMARY OF THE INVENTION
The present invention employs a dedicated loop filter for the acquisition mode and, in addition, uses a second dedicated loop filter for use in the tracking mode. The output of both loop filters are input to a voltage controlled oscillator. As a consequence, two paths for the signal are formed in parallel. Additionally, the output from the acquisition mode low-pass filter is input into the tracking mode low-pass filter.


REFERENCES:
patent: 4200845 (1980-04-01), Mendenhall et al.
patent: 4808884 (1989-02-01), Hull et al.
patent: 5142246 (1992-08-01), Petersson
patent: 5243605 (1993-09-01), Lekmine et al.
patent: 5278703 (1994-01-01), Rub et al.
patent: 5321559 (1994-06-01), Nguyen et al.
patent: 5485472 (1996-01-01), Fredrickson
patent: 5731768 (1998-03-01), Tsang
patent: 5745315 (1998-04-01), Aoyama
patent: 5771127 (1998-06-01), Reed et al.
patent: 5790611 (1998-08-01), Huang et al.
patent: 5936558 (1999-08-01), Shafiee et al.
patent: 5937020 (1999-08-01), Hase et al.
patent: 6292322 (2001-09-01), Haraguchi
patent: 6356129 (2002-03-01), O'Brien et al.
patent: 6606365 (2003-08-01), Chen
F. Dolivo et al, “Fast Timing Recovery for Partial-Response Signaling Systems”, IEEE, 1989, pp. 0573-0577.
Takushi Nishiya et al, “Turbo-EEPRML: An EEPRML4 Channel with an Error-Correcting Post-Processor Designed for 16/17 Rate Quasi—MTR Code”, IEEE, 1998, pp. 2706-2711.
Hamid Shafiee et al, “Low Complexity Viterbi Detection for a Family of Partial Response Systems” IEEE Transactions on Magnetics, vol. 28, No. 5, Sep. 1992, pp. 2892-2894.
Jaekyun Moon et al, “Performance Comparison of Detection Methods in Magnetic Recording” IEEE Transactions on Magnetics, vol. 26, No. 6, Nov. 1990, pp. 3155-3172.
Jan W. M. Bergmans et al, “On the Performance of Data Receivers with a Restricted Detection Delay”, IEEE Transactions on Communications, vol. 42, No. 6 Jun. 1994, pp. 2315-2324.
Younggyun Kim et al, “Delay-Constrained Asymtotically Optimal Detection Using Signal-Space Partioning” IEEE, 1998, pp. 573-577.

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