Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1999-06-23
2001-08-14
Le, Vu (Department: 2713)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C382S234000
Reexamination Certificate
active
06275536
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to transcoding of digital video images, and to particular architectures for using multiple transcoding processors operating in parallel.
The transmission of digital video data, e.g., via broadband communication systems such as cable television or satellite television networks, has become increasingly popular. Digital decoders/set-top boxes are provided in consumers' homes for use in receiving the digital video signals and processing the signals in a format that is suitable for display on a television or video display terminal.
In general, source video sequences can be of any format, e.g., in terms of spatial resolution, frame rate, frame size, color sampling format, interlaced or progressive scan format, bit rate, resolution (e.g., high-definition or standard definition), or amount and type of noise filtering. Additionally, the source video sequences can be pre-encoded at any rate, and with a constant bit rate (CBR) or variable bit rate (VBR).
For many applications, however, the pre-compressed bitstreams must correspond with only specific allowable, or otherwise desirable, video formats and rates. Accordingly, it is often necessary to change the format or other characteristics of the video data prior to communicating it to a set-top box and/or some intermediate point in a network.
The required format changes can be provided by a transcoder. In general, a multi-channel video transcoder is an instrument that converts a set of pre-compressed video bitstreams, such as those conforming to the MPEG standard, into another set of video bitstreams. Such a converting instrument can perform many functions such as changing bit-rate, inserting and dropping bitstreams, transforming resolutions, and bitstream re-multiplexing, etc. Channels of data can be added and dropped. The elementary functional block of such an instrument is a single-channel MPEG-video transcoder.
A straightforward transcoder for an MPEG bitstream can simply be a cascaded MPEG decoder and encoder. The cascaded transcoder first decodes a compressed bitstream to obtain a reconstructed video sequence. The reconstructed video sequence is then re-encoded to obtain a different compressed bitstream that is suitable for transmission. Moreover, more efficient transcoders have been proposed that re-use motion vectors and minimize the changes of macroblock modes.
However, the complexity of the transcoder is still very high, in particular, due to the need for motion estimation of predicted images (e.g., P-pictures and B-pictures). Moreover, real-time transcoding of multiple channels is required. For example, the headend of a cable television network may use a transcoder to combine a satellite feed with local programming in real-time. The processing speed of the transcoder must be sufficient to perform the desired operations without perceptible delays.
Accordingly, it would be desirable to provide a more efficient transcoder architecture. The system should increase processing efficiency by providing multiple transcoding processors. The system should decrease overall processing time, and/or allow the use of lower speed processors.
The system should allow updates to transcoding algorithms to be easily implemented.
The system should accommodate upgrades to new and faster processors (chips) without major re-design.
The system should be more cost effective than specialized transcoding hardware.
The system should be suitable for transcoding multiple channels, such as standard definition video channels, or a single high-bit rate channel, such as an HDTV channel.
The present invention provides a system having the above and other advantages.
SUMMARY OF THE INVENTION
The present invention relates to transcoding of digital video images, and to particular architectures for using multiple transcoding processors operating in parallel.
In a first architecture (architecture A), an input bitstream of n channels is partitioned into processing units, the processing units (such as slices or frames) are split into m sub-streams, and each sub-stream is processed in a corresponding branch. A separate queue is provided for each sub-stream.
In a second architecture (architecture B), the processing units are assigned to any available processor. One queue is provided for all processors.
One option to enhance architecture A is to provide a buffer fullness feedback signal for each of the m branches, and to adjust the splitting of the bitstream such that the incoming data is sent to the emptiest queue (buffer).
With another enhancement for either architecture A or B, the processing units can be re-ordered in the queue(s) according to a shortest-size-first technique.
A further possible enhancement for architecture A, when one or more of the video streams is split into different sub-streams, and for architecture B, is to interleave the frames of different video bitstreams to ensure that every predicted processing unit has its reference processing unit available before the predicted processing unit is first in its queue.
A further possible enhancement for architecture A, when one or more video streams are split into different sub-streams, and for architecture B, is to provide a protection protocol that keeps track of predicted processing units and their correlated reference processing units to ensure that they are not processed at the same time (in different processors). The protection protocol delays the processing of the predicted processing unit until its corresponding reference processing unit has been processed. The transfer of the uncompressed reference processing unit to the processor with the predicted processing unit for motion compensation processing is also coordinated.
By ensuring that correlated processing units are not processed at the same time, a minimum average processing delay can be achieved.
Moreover, the above enhancements can generally be implemented at the same time.
The invention is suitable for transcoding multiple channels, such as standard definition video channels, or a single high-bit rate channel, such as an HDTV channel.
A particular method for transcoding a bitstream of digital video data includes the steps of: partitioning the bitstream into a plurality of successive processing units, queuing the processing units, and assigning each of the queued processing units according to a queuing system model to one of a number of available transcoding processors that are arranged in parallel.
In accordance with the queuing system model, the queued processing units may be assigned to the transcoding processors so that particular ones of the queued processing units that are independent from each other are processed concurrently.
In particular, in accordance with the queuing system model, the queued processing units may be assigned to the transcoding processors such that queued processing units of a reference image and queued processing units from a predicted image thereof are not processed concurrently.
The processing units can be slices, frames, fields, Video Object Planes (VOPs), or Groups of Blocks (GOBs), for example.
For architecture A, in the queuing step, the partitioned processing units are queued in a common queue. In the assigning step, the queued processing units are assigned to the transcoding processors from the common queue. One option here is for the partitioned processing units to be queued in the common queue in a shortest-size-processing unit-first manner.
The processing units may include a processing unit of a reference image, and a processing unit of a predicted image thereof. Moreover, the processing unit of the reference image may be queued in a first queue, and the processing unit of the predicted image is queued in a second, priority queue. After the queued processing unit of the reference image is assigned to the respective transcoding processor for processing, the queued processing unit of the predicted image has priority in being assigned to its respective transcoding processor.
In architecture A, the successive processing units are split into a plurality
Chen Xuemin
Ling Fan
General Instrument Corporation
Le Vu
Lipsitz Barry R.
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