Implementation architecture for performing hierarchical motion a

Details Implementation architecture for performing hierarchical motion a Implementation architecture for performing hierarchical motion a

1992-06-10

1994-01-04

Britton, Howard W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358105, H04N 7137

Patent

active

052765130

ABSTRACT:
First circuit apparatus, comprising a given number of prior-art image-pyramid stages, together with second circuit apparatus, comprising the same given number of novel motion-vector stages, perform cost-effective hierarchical motion analysis (HMA) in real time, with minimum system processing delay and/or employing minimum hardware structure. Specifically, the first and second circuit apparatus, in response to relatively high-resolution image data from an ongoing input series of successive given pixel-density image-data frames that occur at a relatively high frame rate (e.g., 30 frames per second), derives, after a certain processing-system delay, an ongoing output series of successive given pixel-density vector-data frames that occur at the same given frame rate. Each vector-data frame is indicative of image motion occurring between each pair of successive image frames.

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C. Bergeron, E. Dubois, "Gradient Based Algorithms For Block Oriented MAP Estimation of Motion and Application to Motion-Compensated Temporal Interpolation", IEEE Trans. On Circuits And Systems For Video Technology, vol. 1, No. 1, Mar. 1991, pp. 72-85.
K. Metin Uz et al., "Interpolative Multiresolution Coding of Advanced Television with Compatible Subchannels", IEEE Trans. On Circuits And Systems For Video Technology, vol. 1, No. 1, Mar. 1991, pp. 86-98.

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