Implantable medical device incorporating adiabatic...

Details Implantable medical device incorporating adiabatic... Implantable medical device incorporating adiabatic...

2000-02-25

2002-07-02

Evanisko, George R. (Department: 3762)

Surgery: light, thermal, and electrical application

Light, thermal, and electrical application

Electrical therapeutic systems

Reexamination Certificate

active

06415181

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to implantable medical devices, and more particularly to an improved operating system architecture incorporating adiabatic clock-powered logic, alone, or in conjunction with self-timed logic, for reducing power consumption and increasing and improving processing capabilities.
BACKGROUND OF THE INVENTION
A wide variety of implantable medical devices (IMDs) that employ electronic circuitry for providing electrical stimulation of body tissue and/or monitoring a physiologic condition are known in the art. A number of IMDs of various types are known in the art for delivering electrical stimulating pulses to selected body tissue and typically comprise an implantable pulse generator (IPG) for generating the stimulating pulses under prescribed conditions and at least one lead bearing a stimulation electrode for delivering the stimulating pulses to the selected tissue. For example, cardiac pacemakers and implantable cardioverter/defibrillators (ICDs) have been developed for maintaining a desired heart rate during episodes of bradycardia or for applying cardioversion or defibrillation therapies to the heart upon detection of malignant tachyarrhythmias. Other IMDs have been developed for applying electrical stimulation or other therapies, e.g., drugs, to nerves, the brain, muscle groups and other organs and body tissues for treating a variety of conditions.
Over the past 40 years, such IMDs have evolved from relatively bulky, crude, and short-lived devices providing simple stimulation therapies and monitoring functions to complex, long-lived, and miniaturized IMDs, e.g., cardiac IMDs providing a wide variety of pacing and/or cardioversion and defibrillation therapies and/or monitoring functions. Numerous other programmable functions have been incorporated including enhanced capacity to detect and discriminate cardiac arrhythmias, to store data and to uplink telemetry data related to arrhythmia episodes and applied therapies (if any). Moreover, the capability of interrogating stored device data and initiating real time uplink telemetry of physiologic data, e.g. the real time cardiac EGM and blood pressure and the like, have been incorporated into such IMDs.
The earliest implantable pacemaker IPGs employed very simple analog circuit oscillators formed by discrete transistors and other circuit components and were very short-lived and electrically inefficient. Integrated circuit (IC) technology and battery improvements were made that enabled hermetic sealing of IMD housings, improved reliability and lengthened the operating life of the IMD. The MEDTRONIC® SPECTRAX® pacemaker IPGs incorporated an analog IC with digital IC into a digital clocked logic operating system architecture providing an array of sophisticated operating functions, programmability of operating modes and parameters, data storage, and uplink telemetry functions. Successive generations of IMDs of this type have incorporated increased operating modes and functions through further improvements in circuitry and long-lived, low current output, low voltage batteries. Most recently, a wide number of IMD system architectures have been developed that incorporate custom microcomputers comprising a microprocessor, RAM and ROM, bus, and related elements of a typical microcomputer and other control logic, memory, input signal processing circuitry and therapy delivery output circuitry. The complexity of the circuitry, the functions provided, the longevity, and the reliability of the IMDs have all increased dramatically while the IMD size has decreased.
Current IMD operating system architectures typically are embodied in two or more ICs and discrete components mounted to one (or more) substrate employing hybrid fabrication circuitry techniques. Certain of the ICs or circuitry on a particular IC perform analog functions, input signal processing, and output therapy delivery. Digital logic ICs or circuitry are formed employing complementary metal oxide semiconductor (CMOS) fabrication technology. The digital logic ICs perform signal processing, timing, and state change functions embodying Boolean logic timed synchronously by a system-wide, clock, and are referred to herein as “clocked logic” ICs or circuits.
The power consumption of CMOS circuits consists generally of two power consumption factors, namely “dynamic” power consumption and “static” power consumption. The static power consumption is only due to current leakage, as the quiescent current of such circuits is zero. Dynamic power consumption is due to the current required to charge internal and load capacitances during switching, i.e., the charging and discharging of such capacitances, and is the dominant form of power consumption for CMOS technology. The dynamic power (P) for the CMOS circuit is a function of nodal capacitance (C), the clock or switching frequency (F), and the supply voltage (V
DD
) in accordance with the formula P=C V
DD
2
F.
By way of explanation, reference is made
FIG. 1
, which shows a simple CMOS buffer circuit
10
operated using a dual rail clock ø to provide a logic level output at node
22
that is inverse to the applied input. A logic level input signal is provided to the gate terminals of a P-channel MOS (pMOS) FET
14
and N-channel MOS (nMOS) FET
16
, the dual rail clocks are is applied to the gate terminals of a pMOS FET
12
and nMOS FET
18
. Load capacitor
20
is coupled between the node
22
at the source and drain terminals of the pMOS and nMOS FETs
18
and
12
. As will be appreciated, the pMOS FET
14
is biased to switch ON and the nMOS FET
16
is biased to switch OFF when the input is driven LOW, and, conversely, the pMOS FET
14
is biased to switch OFF and the nMOS FET
16
is biased to switch ON when the input is driven HIGH. The nMOS FET
12
is biased to switch ON by the clock ø applied to its gate, and the pMOS FET
18
is biased to switch ON by the inverted clock ø applied to its gate.
The pMOS FET
14
and pMOS FET
18
both switch ON only when the input is driven LOW and when the inverted clock ø occurs. The capacitor
20
is then charged from the voltage source V
DD
, and a logical one (HIGH) is registered at the output (node
22
).
Similarly, the nMOS FET
16
and nMOS FET
12
both switch on only when the input is driven LOW and when the clock ø occurs. The charge stored in the capacitor
20
is then discharged through the nMOS FETs
16
and
12
ground, whereby a logical zero (LOW) is registered at node
22
.
Each transition of the input signal to LOW during the inverted clock ø thereby results in the transfer of a certain amount of energy from the battery supplying V
DD
to capacitor
20
, and that energy is then simply dissipated when the input signal switches HIGH and the clock ø occurs. In addition, the clock energy is itself dissipated during each clock cycle. Thus, in conventional CMOS switches, such as those shown in
FIG. 1
, each transfer of charge is coupled with the dissipation of a certain amount of power (P) in accordance with the above formula.
Efforts have been made conventionally in CMOS IC designs used in IMDs to scale down the supply voltage for an entire device (e.g., a hybrid or IC) to provide the minimally required power to reliably operate all of the clocked logic of the device. For example, in the Medtronic SYMBIOS® pacemaker IPGs, the logic circuitry was powered by a voltage regulator controlling the IC supply voltage to a “sum of thresholds” supply. This regulator provided a supply to the IC (i.e., V
DD
) of several hundred millivolts above the sum of the n-channel and p-channel thresholds of the CMOS transistors making up the IC. This regulator was self calibrating regarding manufacturing variations of the transistor thresholds. This same approach of specifying a high enough voltage to account for fabrication variances is followed even when only a single such CMOS IC is employed in the IMD system. Therefore, in practice, excessive power may be consumed by the CMOS IC or ICs of the IMD operating system.
Other IMDs have reduced power consu

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